Commit graph

13504 commits

Author SHA1 Message Date
Ryan McClelland b7dc01cd48 i3c: rename is_primary to is_secondary
Rename is_primary to is_secondary. The justification for this is
because it is less likely to have something configured to be
secondary, and the 0 value would be if it is primary.

Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
2022-12-12 15:51:16 -05:00
Erwan Gouriou 428700f709 drivers: gpio: stm32: Keep port clock in input configuration
When pin is configured in input mode, clock is also required.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-12-12 15:50:21 -05:00
Ravik Hasija 22e2b004df drivers: serial: Add Driver for CDNS UART IP6528
Adding New Serial/UART driver for Cadence UART IP6528.

Signed-off-by: Ravik Hasija <ravikh@fb.com>
2022-12-12 12:19:35 -05:00
Marco Argiolas 3540ae1df9 drivers: sensor: bmm150: fix mispelling
Build error appearing only when enabling CONFIG_BMM150_PRESET_LOW_POWER

Signed-off-by: Marco Argiolas <marco.argiolas@ftpsolutions.com.au>
2022-12-12 10:54:40 -06:00
Brian Dunlay 491933b185 drivers: wifi: eswifi: Guard net_ctx state change
Previously, a call to set the net_context state was added here to
accommodate a new KConfig scenario that permitted disabling offload
sockets. This code path is used by both local and offloaded sockets.
While it is necessary to update the state of the net_context for a
locally managed socket, setting the net_context for an offloaded socket
is an error, as the net_context is invalid (in fact, it points to a
hard-coded dummy socket), as observed in #52346 and #38544.

A prior commit (a9ac0a88) attempting to remedy the offload socket
scenario removed this line, which resulted in problems for the local
socket scenario. The socket never got updated to the connected state,
and thus was unusable.

Adding this guard allows the eswifi socket to set the socket net_context
only if the socket is NOT offloaded.

Signed-off-by: Brian Dunlay <brian@nubix.io>
2022-12-12 14:55:03 +01:00
Andriy Gelman a9481bdbe1 drivers: gpio_xmc4xxx: Use interrupt controller for edge/level interrupts
Use the XMC4XXX interrupt controller for edge/level gpio interrupts.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2022-12-12 10:51:29 +01:00
Andriy Gelman 727e589448 drivers: interrupt_controller: Add XMC4XXX ERU driver
In Infineon XMC4XXX SoCs, gpio interrupts are triggered via an
Event Request Unit (ERU) module. A subset of the gpios are
connected to the ERU. The ERU monitors edge triggers and creates
a SR.

This driver configures the ERU for a target port/pin combination
for rising/falling edge events. Note that the ERU module does
not generate SR based on the gpio level. Internally the ERU
tracks the *status* of an event. The status is set on a positive
edge and unset on a negative edge (or vice-versa depending on
the configuration). The value of the status is used to implement
a level triggered interrupt; The ISR checks the status flag and
calls the callback function if the status is set.

The ERU configurations for supported port/pin combinations are
stored in a devicetree file dts/arm/infineon/xmc4xxx_x_x-intc.dtsi.
The configurations are stored in the opaque array
uint16 port_line_mapping[].

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2022-12-12 10:51:29 +01:00
Duong Vu Nam b24f4625f0 arch: support nocache for Cortex-R52
Config NOCACHE_MEMORY depend on ARCH_HAS_NOCACHE_MEMORY_SUPPORT. Enable
ARCH_HAS_NOCACHE_MEMORY_SUPPORT for Cortex-R52 to run NXP S32Z/E with
nocache attibute.

Enable nocache in each driver use it.

Signed-off-by: Duong Vu Nam <duong.vunam@nxp.com>
2022-12-12 10:39:31 +01:00
TOKITA Hiroshi e965db984d samples: counter: alarm: add support for GD32 boards
Add support for boards that implements the GD32 SoCs.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2022-12-12 10:08:12 +01:00
TOKITA Hiroshi 981d88bf7b drivers: counter: add support for GD32 timer
Adds support for GD32 timer

Note: Currently, it is not supporting RISC-V(GD32V) devices.
It needs some work on the interrupt controller first.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2022-12-12 10:08:12 +01:00
TOKITA Hiroshi d38a1fe2fa drivers: clock_control: gd32: timer should recognize with entire id
The timer_ids contain timers that belong to any bus.
So, It should recognize with entire id, not only the CLOCK_ID_BIT part.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2022-12-12 10:08:12 +01:00
TOKITA Hiroshi 79451c221a drivers: clock_control: gd32: Correcting timer node detection
DT_COMPAT_GET_ANY_STATUS_OKAY is not suited for the node's existing check.
(This macro returns the stem of the DTS macro name,
 the stem part is not a defined symbol.)
Instead, it should use the DT_HAS_COMPAT_STATUS_OKAY macro.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2022-12-12 10:08:12 +01:00
Ravik Hasija 96da6f2234 driver: dw: Use base_addr variable to set dir.
Change Summary:
Update Base addr to set direction to use Aligned IP base address instead
of Port Base Address. Port Base Address + offset to direction register
will set incorrect value for Port B,C & D. For ex: In cases when more than
1 port is configured on the same IP, the DTS node for port B will start
at offset 0xC. Calculating the port using Port Base will yield offset of
PORTB DIR register which is at offset 0x10 from Aligned Base, and as a
result will result in setting DIR register of PORTC instead.

Signed-off-by: Ravik Hasija <ravikh@fb.com>
2022-12-11 20:37:33 -05:00
Ravik Hasija 7ba1925d97 driver: gpio: Fixing Pin Direction Setting.
Change Summary:
Moving the setting of Pin direction before setting/clearing the pin
configured as output for the change to correctly take place.

Signed-off-by: Ravik Hasija <ravikh@fb.com>
2022-12-11 20:37:33 -05:00
Rodrigo Cataldo bcb3961567 drivers: pcie: late initialization of pcie when PCIe controller is used
For architectures that rely on a PCIe controller (for example, ARM64),
scanning the PCI space will only succeed after the controller has
initialized. Therefore, in the presence of PCIe controller, the PCIe
initialization is bumped to the next system init level.

In the past, drivers like ivshmem would do a late scan of the PCI space
in case the early scan failed; however, the cited commit removed this
feature and ivshmem fails for ARM64. This commit fix this by making the
early scan succeed.

Fixes: a96016d747 ("drivers: ivshmem: Remove unnecessary BDF lookup ...")
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
2022-12-10 09:47:26 +01:00
Rodrigo Cataldo 0efb0f55b3 drivers: ivshmem: msi.h header only required for ivshmem-doorbell
Only include the MSI header when ivshmem-doorbell is employed, as the
ivshmem data structures already use the same protection for msi-related
structures.

Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
2022-12-10 09:47:26 +01:00
Rodrigo Cataldo eb4dee62c5 drivers: ivshmem: remove unnecessary platform dependency
The ivshmem code does not use any platform-specific code; therefore,
remove the dependency to the soc interface.

No functional change intended.

Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
2022-12-10 09:47:26 +01:00
Andrzej Głąbek 1a6e26db33 drivers: i2c_nrfx_twi[m]: Make transfer timeout value configurable
Add a Kconfig option allowing users to configure the transfer timeout
value, as the default 500 ms may not be sufficient in specific cases.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2022-12-10 09:46:45 +01:00
Patryk Duda 1aebcec02f drivers: serial: Reset UART using RCC before initialization
In multi-image environment, after jump to the image we can have UART in
unexpected state. Reset UART to default state to make sure that UART is
initialized properly and won't cause system to crash or hang.

Signed-off-by: Patryk Duda <pdk@semihalf.com>
2022-12-09 09:43:36 -08:00
Patryk Duda 227ac76828 drivers: counter: Reset timer using RCC before initialization
In multi-image environment, after jump to the image we can have running
timer with interrupts enabled. If interrupt is triggered, the asserts
in the driver can cause a crash.

This patch also adds 'resets' property for all timer nodes.

Signed-off-by: Patryk Duda <pdk@semihalf.com>
2022-12-09 09:43:36 -08:00
Patryk Duda 3cbbcefb12 drivers: reset: Add support for reset clear register
To deassert reset in STM32MP1 RCC the driver needs to set the bit in
reset clear register.

This patch extends existing implementation to support this type of
register.

Signed-off-by: Patryk Duda <pdk@semihalf.com>
2022-12-09 09:43:36 -08:00
Patryk Duda d6f8e9ae5b drivers: reset: Introduce STM32 reset controller
This driver exposes STM32 RCC reset functionality through reset API.

Information about RCC register offset and bit is encoded just like GD32.
The first 5 least significant bits contains register bit number.
Next 12 bits are used to keep RCC register offset. Remaining bits are
unused.

Signed-off-by: Patryk Duda <pdk@semihalf.com>
2022-12-09 09:43:36 -08:00
Patryk Duda e4b8dce1e5 drivers: dma: Simplify stm32_dma_check_fifo_mburst() function
This function is responsible for checking if combination of msize,
mburst and FIFO level is allowed. Possible combinations can be found in
ST documentation, eg. Table 36. FIFO threshold configurations, RM0402
9.3.13 FIFO chapter.

Previously there was no 'break' or '__fallthrough' in msize switch which
caused compilation errors. Since we are confirming that combination is
correct, 'break' statements should be used.

Besides of introducing missing 'break' statements, this patch moves
'return false' from switch to the end of the function. This makes code
shorter and easier to understand, because we have only correct
combinations.

Signed-off-by: Patryk Duda <pdk@semihalf.com>
2022-12-09 11:18:01 +01:00
Filip Brozovic c60e100ab3 drivers: serial: numicro: fix poll_in function
The poll_in function of the NuMicro UART driver was using the UART_Read
function from the Nuvoton HAL, which is blocking. Replace it with a
non-blocking implementation.

Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
2022-12-08 18:46:33 +01:00
Filip Brozovic 617aa8cc65 drivers: serial: numicro: use pinctrl instead of hard-coded values
This commit enables the numicro serial driver to configure the UART
pins using the pinctrl API.

Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
2022-12-08 18:46:33 +01:00
Filip Brozovic 3453a3b247 drivers: pinctrl: add numicro pinctrl driver
This commit adds a pinctrl driver for the Nuvoton NuMicro family
of processors.

Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
2022-12-08 18:46:33 +01:00
Filip Brozovic 8577bb3e84 drivers: gpio: add driver for nuvoton numicro
This commit adds a GPIO driver for the Nuvoton NuMicro family
of processors.

Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
2022-12-08 18:46:33 +01:00
Francois Ramu 9c49ee3e48 drivers: dma: stm32u5 dma with resume API function
Add the resume API function for the dma driver of the stm32U5 serie.
That completes the suspend API function.
Controlling the SUSPF bit of the GPDMA CR register is enough
to suspend/resume the channel.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-12-08 14:59:01 +00:00
Francois Ramu e5306ed8e3 drivers: dma: stm32u5 do not reset the dma channel when suspending
There is no need to reset the channel else DMA config is lost and
channel should be enabled again in case of resume.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-12-08 14:59:01 +00:00
Georgij Cernysiov 581a50e000 drivers: usb: stm32: Simplify Kconfig help message
The USB_DC_STM32 help message started to miss some
STM32 MCU families. Overtime, the message will
get bigger if we continue to list family names.
Removed family names to simplify the message and
avoid periodic modifications.

Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
2022-12-08 09:58:58 +00:00
Maciej Zagrabski e31c0d0ff4 Revert "drivers: gpio: STM32U5 independant IO supply"
This is already fixed in zephyrproject-rtos/hal_stm32#147.

This reverts commit 5b4ad9127f.

Signed-off-by: Maciej Zagrabski <mzi@trackunit.com>
2022-12-08 09:56:35 +00:00
Patryk Duda f7fca220ba drivers: bbram: Introduce BBRAM shell
Add 'bbram' command which is very convenient tool for examining and
modyfying BBRAM content.

Examples:

Write one byte:
$ bbram write backup_regs 0x1 0xaa

Write many bytes (starting from 0x13):
$ bbram write backup_regs 0x13 0xa 0xb 0xc 0xd 0xe 0xf 0xaa 0xab 0xac

Read whole BBRAM:
$ bbram read backup_regs

Read many bytes (4 bytes starting from address 0x14 in this case):
$ bbram read backup_regs 0x14 4

Read one byte (from 0x14 address):
$ bbram read backup_regs 0x14

Signed-off-by: Patryk Duda <pdk@semihalf.com>
2022-12-08 16:47:09 +09:00
Patryk Duda e02456a52d drivers: bbram: Introduce STM32 BBRAM driver
STM32 battery-backed RAM is organized in 4 byte registers. Number of
registers can vary between models from 5 to 32 registers.

Usually, the registers are part of RTC. On some variants they are part
of tamper module. On STM32F1 the registers are in separate module. For
now, only backup registers from RTC are supported.

Signed-off-by: Patryk Duda <pdk@semihalf.com>
2022-12-08 16:47:09 +09:00
Bartosz Bilas e077fb73ec drivers: tests: replace usage of spi_is_ready with spi_is_ready_dt
`spi_is_ready` function is being deprecated in favor of
`spi_is_ready_dt` so let's replace the old usage in the tree.

Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
2022-12-07 09:40:23 -06:00
Patryk Duda a9ed11ab8d drivers: counter: Add __fallthrough in STM32 counter driver
STM32 counter driver uses switch statement in which cases don't end
with break or return intentionally.

Affected switches in counter driver check status of all timer channels
(maximum 4 channels), but the number of channels is not determined
during compilation. In switch, we jump to channel with highest number
and then check other channels with lower numbers.

Compiler can warn about it, so this patch adds information that it was
intentional.

Signed-off-by: Patryk Duda <pdk@semihalf.com>
2022-12-07 14:26:42 +00:00
Maciej Zagrabski ec7237c38a drivers: gsm_ppp: replace DT_INST with DT_DRV_INST
Replace error prone DT_INST with proper DT_DRV_INST.

Signed-off-by: Maciej Zagrabski <mzi@trackunit.com>
2022-12-07 10:29:34 +00:00
Lucas Tamborrino b196edf55d drivers: spi: esp32xx: Fix buffer length for DMA
Fixes #52588

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2022-12-07 10:13:38 +00:00
Grixa Yrev 4fe862e396 drivers: lpuart: enable rs485 mode
NXP LPUART IP supports rs485 mode when transceiver driver enable
using RTS. Allow setting rs485 mode up via the "nxp,rs485-mode"
dts property. "nxp,rs485-de-active-low" dts property can be used
for set RTS polarity.

Signed-off-by: Grixa Yrev <GrixaYrev@yandex.ru>
2022-12-07 10:12:14 +00:00
Francois Ramu 2ed292e1be drivers: stm32: do not enable the HSI48 locally
The HSI48 is enabled by clock control driver.
It is no more done by each driver that requires this clock
However when using rng or sdmmc or bluetooth/ipm or usb,
the HSI48 clock must be present in the DTS.
Add a warning for this particular check but keep the deprecated
HSI48 clock enable : keeping for legacy but to remove later.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-12-07 10:03:11 +00:00
Francois Ramu 8eb55b3416 drivers: clock_control: some stm32 have a HSI48 fixed clock
For the stm32 devices that have a HSI48 clock,
the driver enables it, like any other fixed clock,
if needed and supported by the serie.
For stm32L0, SYSCFG VREFINT is also required.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-12-07 10:03:11 +00:00
Michał Barnaś 23a04b8b0a gpio: cleanup the nct38xx driver
Reorganize includes and fix the indentation of code.

Signed-off-by: Michał Barnaś <mb@semihalf.com>
2022-12-06 10:10:36 -05:00
Michał Barnaś 59766b52be gpio: add support for get_config and get_direction in nct38xx
This commit adds support for get_config and get_direction functions
for the nct38xx IO expander family.
Also applies the clang-format changes.

Signed-off-by: Michał Barnaś <mb@semihalf.com>
2022-12-06 10:10:36 -05:00
Michał Barnaś c11af96135 gpio: fix the nct38xx driver
This commit fixes the comment and adds the missing assignment of
return value from i2c read byte command in the nct38xx driver.

Signed-off-by: Michał Barnaś <mb@semihalf.com>
2022-12-06 10:10:36 -05:00
Daniel DeGrasse 7d1f435a2a drivers: ipc: Enable messaging unit driver for iMX.RT multicore SOCs
Enable MU messaging unit driver for RT11xx socs.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-12-05 19:54:37 +01:00
Gerard Marull-Paretas 649a8195b3 drivers: regulator: pca9420: refactor mode handling
- Similar to what was done for other parts of the driver, remove any
  register specification from Devicetree (modesel-reg/mask)
- Keep all the information in the driver, and define modes as "numbers",
  e.g. PCA9420_MODE0: 0, PCA9420_MODE1: 1, etc.
- Bindings provide IC defaults now (all modes allowed 0/1/2/3 and
  initial mode set to 0).
- When mode is controlled via the MODESEL0/1 pins (ie directly by an iMX
  MCU using the dedicated PMIC_MODE0/1 pins), the driver will not allow
  to select a mode (it is not possible). This mode is now enabled by
  setting `nxp,enable-modesel-pins` in Devicetree. When enabled, all the
  allowed modes are configured to be selectable via pins. When disabled,
  mode can be set via I2C (using TOP_CNTL3 MODE0/1_I2C fields)

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-12-05 19:10:55 +01:00
Xinyang Tan 535f5a6c04 shell: support setting help string for each entry in a dictionary command
Add support for setting the help description for each entry in a dictionary
command. Currently the syntax string alone may not provide sufficient
description of its entry. This commit also helps keep the help messages
consistent with existing style.

Signed-off-by: Xinyang Tan <xinyang.tan@delve.com>
2022-12-05 18:40:46 +01:00
Bjarne von Horn e24e6454e9 drivers: ethernet: stm32: initialization routine for the new driver
Setup has to be adapted, too

Signed-off-by: Bjarne von Horn <B.von_horn@wzl.rwth-aachen.de>
2022-12-05 18:31:38 +01:00
Bjarne von Horn aa5353a901 drivers: ethernet: stm32: Enable receiving with new driver
Use the new API in the receive method

Signed-off-by: Bjarne von Horn <B.von_horn@wzl.rwth-aachen.de>
2022-12-05 18:31:38 +01:00
Bjarne von Horn 202abc9acc drivers: ethernet: stm32: Transmit frames larger than one buffer
Now, multiple tx buffers can be used to send packets,
so that the packet size can exceed tx buffer size.

Signed-off-by: Bjarne von Horn <B.von_horn@wzl.rwth-aachen.de>
2022-12-05 18:31:38 +01:00
Bjarne von Horn 1a9420af8d drivers: ethernet: stm32: Enable transmitting with new driver
Use the new API in the transmit method

Signed-off-by: Bjarne von Horn <B.von_horn@wzl.rwth-aachen.de>
2022-12-05 18:31:38 +01:00