3 commits

Author	SHA1	Message	Date
Yong Cong Sin	39433f0669	drivers: intc: plic: define all registers' offset in the driver ... Define all the register offset directly in the driver according to the RISCV PLIC specification as they are not configurable, see: https://github.com/riscv/riscv-plic-spec. Updated devicetrees that has PLIC accordingly. Signed-off-by: Yong Cong Sin <ycsin@meta.com>	2023-10-04 09:06:28 -04:00
Filip Kokosinski	806c95163a	dts/riscv: add missing riscv,isa fields and modify existing ones ... This commit adds/modifies `riscv,isa` strings using the following rules: * the ISA string is lowercase * multi-letter extensions are preceded with the underscore mark * if an extension is implied by another one, it is not specified - e.g. the D extension implies the F extension, so writing `rv32ifd` is redundant Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>	2023-09-14 14:34:34 +02:00
Manojkumar Subramaniam	80fda53492	dts: riscv: add a initial SoC dtsi for Efinix Sapphire SoC ... Sapphire SoC from Efinix Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>	2023-06-27 12:09:57 +00:00