Define all the register offset directly in the driver according
to the RISCV PLIC specification as they are not configurable,
see: https://github.com/riscv/riscv-plic-spec.
Updated devicetrees that has PLIC accordingly.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
This commit adds/modifies `riscv,isa` strings using the following rules:
* the ISA string is lowercase
* multi-letter extensions are preceded with the underscore mark
* if an extension is implied by another one, it is not specified - e.g. the
D extension implies the F extension, so writing `rv32ifd` is redundant
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Use the sifive,clint0 compatible instead of "riscv,clint0" and remove
interrupt controller fields (clint compatible is used for its timer
registers). Refer to the Linux or previous commits for more context.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This mirrors #36499 and other PRs that added them for other
architectures.
This silences a large number of dtc warnings due to the missing
property. It seems reasonable to require an address-cells property since
any interrupt controller could be the parent of an interrupt-map.
The only device actually using interrupt-maps is neorv32, and it needs
an address-cells of 2 (since this is the default if none is specified it
worked like that before this change).
While I touched this, I reordered the properties for consistency across
boards, but there's a lot of variance here already.
Signed-off-by: Olof Johansson <olof@lixom.net>
In 8f9290d2741844 ('dts: bindings: riscv: Add and use bindings for
sifive CPUs'), new compat strings for SiFive CPUs were added, but with
riscv prefixes. Vendor-specific compats should just be prefixed with the
vendor, so move that over here.
Fixes: 8f9290d2741844 ('dts: bindings: riscv: Add and use bindings
for sifive CPUs')
Signed-off-by: Olof Johansson <olof@lixom.net>
