This commit attempts to split the generic i.MX8 SoC into its
QXP and QM variants. As things are now, the i.MX8 SoC doesn't
have any NXP HAL files to back it up. As a consequence, the
native Zephyr drivers cannot be used.
To solve this issue, the generic i.MX8 has been split into
i.MX8QXP and i.MX8QM, each of them having different NXP HAL
files.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add drivers for gpio_i2c_switch which is present in beagleconnect freedom
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
Signed-off-by: Ayush Singh <ayushdevel1325@gmail.com>
Commit 944ced68f5 enabled
CONFIG_UART_CONSOLE=y for the beagleconnect_freedom board, which had the
side effect of satisfying a required dependency for the sensor shell
sample application and causing new build errors in the weekly full
twister run. Fix the build errors by moving the board's light and
humidity sensor nodes to be children of the I2C controller node.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
This board HW models do not yet support the NFCT peripheral,
let's remove the DT node to avoid the driver being selected.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This patch removes the now unused scratch partition and enlarges
the application slots instead.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
This commit enables clock control instances for apollo4p_blue_kxr_evb.
Also adds pin configuration for each instance.
Signed-off-by: Aaron Ye <aye@ambiq.com>
This is support for AArch64 development board.
The board uses 4-core Cortex-A55, which are based on
the ARMv8.2 architecture.
In addition,we support smp support and
it can use 4-cores to run basic samples.
Signed-off-by: Charlie Xiong <1981639884@qq.com>
Enable ticket spinlock on nsim SMP board as they are
naturally vulnerable to spinlock unfairness due to
SMP nSIM way of work.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Add in DT the possibility to configure both INT1 and INT2
pin. The driver will then assign one of the two (either 1
or 2, according to what value drdy_pin is set) to a gpio
for receiving drdy interrupts.
The other pin may be used in the future to receive event
interrupts.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Commit c6e3bac4f changed the core clock frequency of LPC55XXX series.
That clock is used by the cortex-m systick timer, which is the
default timer used for system time in zephyr on this series.
The bug is that the config SYS_CLOCK_HW_CYCLES_PER_SEC default was not
updated on the affected platforms to account for this change, so system
time is currently recorded as 150% of reality. Fix this by changing the
kconfig to be set automatically at SOC level and remove board defaults.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This chip uses an active low reset, so the correct behavior here is to
define the pin as ACTIVE_LOW, using GPIO_OUTPUT_ACTIVE to assert the
reset and set to 0 to deassert.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This chip uses an active low reset, so the correct behavior here is to
define the pin as ACTIVE_LOW, using GPIO_OUTPUT_ACTIVE to assert the
reset and set to 0 to deassert.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Basic spinlock implementation is based on single
atomic variable and doesn't guarantee locking fairness
across multiple CPUs. It's even possible that single CPU
will win the contention every time which will result
in a live-lock.
Ticket spinlocks provide a FIFO order of lock aquisition
which resolves such unfairness issue at the cost of slightly
increased memory footprint.
Signed-off-by: Alexander Razinkov <alexander.razinkov@syntacore.com>
The sfdp table property is no more required in the DTS of the
stm32h7b3i_dk as it is correctly read from the external
NOR octoflash with the read-sfdp command.
(since PR https://github.com/zephyrproject-rtos/zephyr/pull/62521)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This adds the required conf and dts overlays required for the
application on stm32h747i-disco board.
Also moved CONFIG_SDMMC_STM32_HWFC option from prj_blk.conf to
nucleo_h743zi_blk.conf as that is STM specific option.
Build the application as
west build -p always -b stm32h747i_disco_m7 \
samples/subsys/fs/littlefs/ -- \
-DOVERLAY_CONFIG=boards/stm32h747i_disco_m7.conf -DCONF_FILE=prj_blk.conf
Signed-off-by: Murali Karicheri <murali.karicheri@sandc.com>
STM32L562 Discovery kit is not compatible with Bluetooth over USB
application.
Add missing information related to the BLE capability of this board.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Modify SPI configuration to match the features introduced in PR #63437.
Set the property "controller-data-delay-us" to zero for boards
which are using BlueNRG-MS.
Fix Chip Select configuration for stm32l562e_dk board.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Adds the device trees for the board and its Arduino connector,
default Kconfig and documentation.
The following features have been confirmed working on hardware:
* ADC
* I2C
* RTC
* SPI
* SDMMC
* UART
* OctoSPI Flash
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
This makes intel_rpl board configuration similar to other Intel
boards (like intel_adl) and also fixes SHELL_STACK_SIZE configuration.
It should depend on ACPI.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
axp192 is used by the display controller and gpio hog subsys
thus we need to set this priority to the smaller value.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
The workqueue test may intermittently fail, with errors such as:
work_1cpu_test_1cpu_system_schedule: (elapsed_ms <= max_ms is false)
long 102 > 101
Disabling PM makes the issues go away, and it is what this patch does.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Instead of those set, use the default ones
for the MFD/REGULATOR_AXP192_INIT_PRIORITY/GPIO_AXP192_INIT_PRIORITY
that are set to the 80/86/81 values correctly. Adjust the
GPIO_HOGS_INIT_PRIORITY only to be executed after GPIO driver.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
Fix MCUBoot error for LPC55S69 "slots are not compatible".
Use the standard slot naming,
used by TFM-enabled Zephyr platforms.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
The existing driver and sample:
- drivers/bluetooth/hci/rpmsg
- samples/bluetooth/hci_rpmsg
are no longer correctly named, since they now use the IPC subsystem to
send and receive data. The IPC subsystem can use RPMsg as a transport,
but that is one of several selectable backends.
I initially wanted to deprecated both the BT_RPMSG Kconfig option as
well as the zephyr,bt-hci-rpmsg-ipc chosen node in Devicetree. However,
this proved to be undoable in the case of the Kconfig option. This is
because it's a choice option, and those have special behavior. In
particular, the only practical way to deprecate would've been to keep
the old Kconfig option outside the choice (much like it's done in this
commit) but then also add a 'depends on !BT_RPMSG' on each of the
remaining choice symbols *except* on the new BT_HCI_IPC one. This, however,
only works correctly for .conf files. If a board instead sets the
default BT_HCI_BUS_TYPE in the Kconfig.defconfig file then the Kconfig
tree parsing would fail, because it'd try to set it to a value
(BT_RPMSG) that is no longer part of the choice.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Unify spelling of CAN Flexible Data-rate abbreviation to "CAN FD" instead
of "CAN-FD". The former aligns with the CAN in Automation (CiA)
recommendation.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add support for the Arduino UNO R4 Minima.
This board is the newest version of Arduino that uses Renesas RA4M1 SoC.
This commit provides only limited support to simplify the initial
support patch.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
The PRT bus name for most (especially older) platforms is _SB.PCI0. Only
newer platforms use something else (like _SB.PC00).
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
ACPICA initialization takes considerably more than 32k. E.g. on
up_squared the utilization is 400-500k, qemu_x86_64 about 120k and on
EHL about 1.5M. Increase the default on these platforms to be big enough
if ACPI is enabled.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
`cs-gpios = <&gpio1 23 0>;` is incorrect, since pin P1.23 does not even
exist in nRF52833. According to schematic, it should be P0.23 and this
CS line should be configured as active low.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Serpente schematic has the same clocking arrangement as
boards/arm/adafruit_trinket_m0. This fix copies the clocking
config from the trinket.
Fixes https://github.com/zephyrproject-rtos/zephyr/issues/64470
Signed-off-by: Tom Keddie <github@bronwenandtom.com>
In the documentation recently started to appear ':orphan:', which is
marking for orphaned page. Use start-after to include after marking.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Enable using a BlackMagicProbe for flashing and debugging XIAO BLE
boards.
Tested successfully with BMP 1.9.2 running on ST-Link/v2 against a
`xiao_ble` board.
Signed-off-by: Augusto Zanellato <augusto.zanellato@gmail.com>
Add support for these two options in the simulated board.
Before these options were otherwise defined in the real
BOARD/SOC kconfig files, which meant samples/tests which
used them would not be able to build due to a kconfig error.
With this change they can both be selected, and the right
functionality is built in.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The header file defines macros that are not used in the boards dts but on
the SoC level. They should be include where they are used.
Signed-off-by: Franciszek Zdobylak <fzdobylak@antmicro.com>
for nucleo_stm32g0b1 board.
the HSI48 clock is the clock used by default for the USB controller,
however its default tolerance is not enough for the USB specification,
leading to some random errors depending on many factors, including the
upstream HUB or host.
this commit adds an option in the device tree to enable the STM32 Clock
recovery system (CRS) using USB SOF packet reception as a reference,
which brings the HSI48 within the required accuracy for USB transfers.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
Make NXP S32 Debug Probe runner the default on this board and keep
Lauterbach TRACE32 runner as an alternative.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The NXP S32 Debug Probe is a JTAG-based probe that enables debugging on
NXP S32 devices. This probe is designed to work in conjunction with NXP
S32 Design Studio and this runner offers a wrapper to launch a debug
session from cli.
`flash` command is not implemented at the moment because presently there
are no zephyr boards that can make use of it and test it.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Define the CONFIG_STM32_LPTIM_CLOCK_LSE when the board DTS
has STM32_SRC_LSE has lptim clock source.
CONFIG_STM32_LPTIM_CLOCK_LSI is defined by default.
The CONFIG_SYS_CLOCK_TICKS_PER_SEC is set by soc/arm/st_stm32/common/
Kconfig.defconfig.series.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The stm32h735g_disco board support Ethernet but the L2 Ethernet driver
was not being enabled.
The L2 Ethernet driver is now enabled along with Networking.
Signed-off-by: Ben Marsh <ben.marsh@helvar.com>
OpenOCD can now be used to flash and debug nucleo_wba52cg.
However, today, it requires use of recent upstream OpenOCD.
Add instructions on how to proceed.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
M5Stack-Core2 comes with a base shield that is connected to the M5Stack
extention connector. It features a MPU6886 6-axis motion tracker
and a SPM1423 microphone.
Signed-off-by: Martin Kiepfer <m.kiepfer@teleschirm.org>
Before we were defining the buffer in the runner context
which is simpler and less error prone, but it had a hardcoded
size decoupled from DT as it could not be based on DT
information.
Instead, let's allocate the buffer in the application core
image. This allows us to size it based on the device tree
configuration.
Note that this then requires the application core image
to be present during link time of the final executable
when the IPC subsystem is used.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Fix secure and non-secure images overlapping because of incompatible
flash layout configurations.
Align the board configurations to match the nRF9160 DK default
partition layout.
This enforces that the SPU alignment requirement is satisfied for
the nrf9160 MCU.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
For the 5340 simulated boards:
* Now that the HW models include the IPC and MUTEX peripherals
we can enable them in DT.
* Also enable the DT mbox definition and allocate its shared memory
* Set the default kconfiguration for the HEAD, IPC, MBOX and split
BT stack as in the equivalent real targets.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Provide the actual shared memory buffer for the
IPC rpmsg backend in this platform.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Each MCU initialization hooks will attempt to call
into the API to connect to the bsim phy and, if the
user requested it thru command line, delay its boot.
Doing this for all MCUs is best to ensure it is done
even if there is no image for the other MCU,
but results in the calls being done twice if there is
2 MCUs images, which results in the simulator API giving
a warning about it being likely an error in the app.
To avoid this problem, let's have this be called
only once.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The BCM2711 SoC exposes 58 GPIOs. The first 28 (bank 0) are accessible
to users via the 40-pin header, while the others (bank 1) are used for
controlling on-board peripherals.
This also update doc of `rpi_4b` board.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
* defconfig is located under `boards/arm64/` instead of `boards/arm/`
* 64-bit mode (`arm_64bit=1`) is required to boot
Signed-off-by: Chen Xingyu <hi@xingrz.me>
Add uart1 pin assignment for the raytac_mdbt53v_db_40_nrf5340 board.
This is required in order to support building TF-M for the NS variant.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Add HW flow control pins for raytac_mdbt53_db_40_nrf5340 board.
Use the same pins as the cpunet has been assigned, as the RX / TX lines
was also using the same as cpunet.
Remove bias-pull-up as uart1 using same pins on cpunet does not have
this either.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Add uart1 pinctrl assignment to nrf5340 Audio DK.
Assigned according to Schematic for this board.
Uart1 pins needed by TF-M when using the NS board variant.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
For GPIO pins above 31, one needs to use the `&gpio1` (or similar)
definition, as zephyr seperates GPIOs into chunks of 32.
Signed-off-by: Sophie 'Tyalie' Friedrich <dev@flowerpot.me>
Previously the seed connector was defined incorrectly and as such D6 and D7
weren't usable as i.e. inputs. Zephyr distinguishes GPIO pins in blocks of
32, a distinction the ESP32 reference manual doesn't do. As such one needs
to write `&gpio1 11` in order to access `GPIO43`.
Signed-off-by: Sophie 'Tyalie' Friedrich <dev@flowerpot.me>
The counter_native_posix driver currently does not support top value
configuration, i.e. `ctr_set_top_value` returns `-ENOTSUP`. This commit
adds support for top value configuration, and with the counter API now
fully implemented, adds `counter` to `supported` peripherals for
native_posix target.
It also resolves an existing bug in which the
counter ISR did not reset upon reaching `TOP_VALUE`.
And adds support for multiple channels
Signed-off-by: Jason Wright <jason@jpw.nyc>
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The PAN1783 evaluation board is a development tool for the nRF5340
from Nordic Semiconductor.
Signed-off-by: Steffen Jahnke <steffen.jahnke@eu.panasonic.com>
The nRF52840 MDK USB Dongle board selects the `uart0` node as
`zephyr,console` in the `chosen` node. This required three additional
options to be y-selected on Kconfig side so that printf/stdout etc. hooks
are properly installed:
* CONFIG_CONSOLE
* CONFIG_SERIAL
* CONFIG_UART_CONSOLE
Without that, no console output is observed.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The MikroE clicker 2 board selects the `uart4` node as `zephyr,console` in
the `chosen` node. This required one additional option to be y-selected on
Kconfig side so that printf/stdout etc. hooks are properly installed:
* CONFIG_UART_CONSOLE
Without that, no console output is observed.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The Ruuvitag board selects the `uart0` node as `zephyr,console` in the
`chosen` node. This required three options to be y-selected on Kconfig side
so that printf/stdout etc. hooks are properly installed:
* CONFIG_CONSOLE
* CONFIG_SERIAL
* CONFIG_UART_CONSOLE
Without that, no console output is observed.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The bstests code builds and executes with the embedded
code, but had a call into "free()" which, when building
the embedded code with an embedded C library lands
in the embedded libC free, while it should
always call into the host libC free.
Fix it by calling thru the appropriate trampoline.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
By providing a devicetree stub file, we make sure some internal macros
required by devicetree.h are generated in devicetree_generated.h. This
makes sure that systems without devicetree can continue working without
extra ifdeffery.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add ADC support for longan nano.
Tested using samples/drivers/adc. Also added longan_nano.overlay
and updated documentation.
Signed-off-by: Maxin John <maxin.john@gmail.com>
Add QEMU_EXTRA_FLAGS as QEMU board config option.
This allows Twister tests to provide additional device setup
commands to QEMU in prj.conf or testcase.yaml configuration files.
Example use case: to setup TCP or UDP network interfaces
with non-conflicting port numbers in different test suites
to avoid conflicts when Twister run tests in parallel on the
same host.
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
Remove the mention of startup script and update the documentation
to reflect the current way of working i.e., using net-setup.sh script
before starting the zephyr.exe process.
Signed-off-by: Jukka Rissanen <jukka.rissanen@nordicsemi.no>
This changes qemu_xtensa to use dc233c core instead of
sample_controller. The sample_controller uses a very
basic configuration which lacks features usually needed
in real world applications. Instead, use the dc233c core
as the base for qemu_xtensa so we can use QEMU to cover
more of our code path.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add shield definition for the MikroElektronika ACCEL 13 Click.
The ACCEL 13 Click carries a IIS2DLPC ultra-low power triaxial
accelerometer sensor in a mikroBUS form factor.
Signed-off-by: Mark Olsson <mark@markolsson.se>
The nucleo_g431rb board is equipped with STM32G491RE microcontroller,
which do have the RNG IP block.
However, by default it is not enabled. To make it working properly, the
provided clock needs to fulfill following condition:
fRNGCLK < fHCLK/32, otherwise RNG_SR would set CEIS (bit5) and CECS
(bit1).
When combined with enabled interrupt from RNG, one would experience the
interrupt storm.
In this patch the DTS for this board has been adjusted properly, as well
as the board description has been updated to reflect RNG support.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This commit adds board files for the da14695_dk_usb.
The board features two Mikrobus sockets, these are added to the dts
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
Add the following XPRO boards to flash driver test:
SAMD20, SAMDE54 and SAMR21
Signed-off-by: Daniel Evans <photonthunder@gmail.com>
Co-authored-by: Gerson Fernando Budke nandojve@gmail.com
Fix typo in nsim_hs6x_smp_12cores platform name (as previously
we had nsim_hs5x_smp_12cores platform mentioned two times)
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Make sure devicetree, kconfig, etc. code snippets all have proper
pygments language set.
Note: only existing code-block:: directives have been updated. Another
pass should be made to address implicit code-blocks (`::`)
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The inclusion of this note in the migration guide
explains the clocking change that occured in the
LPC55XXX soc as well as the added Kconfig that toggles
the PLL1 from being initialized. Also updated the
lpc board docs to state the correct System
Clock Value.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
This image was accidentally shrunk too much in
e81e92dbb9.
Restore the previous version.
Fixes#64021
Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
Added overlay inside the spi loopback test for the
mimxrt1170_evk_cm7, enabled DMA and Async by default.
Added testcase for async and dma.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Enhance the documentation by providing an explanation of WKPU
interrupt controller support and how it integrates with GPIO.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Do not declare the in5 on pin PA0 of the adc1 since it makes
conflict with uart4_tx_pa0.
Other ADC1 adc1_in1_pc0 or adc1_in2_pc1 are not available
(used by the i2c3).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Update documentation for core clock frequency on LPC55xxx boards, to
indicate that they are clocked from PLL1 at 150MHz by default. Add a
note about the reduction to 96MHz required when using the flash
controller.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The tsim executable is named tsim-leon3, tsim-leon4, tsim-gr716, etc.
This is needed to find the emulator program for twister to do the run
step.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Since frdm_k64f is used as example in mcumgr sample with serial transport,
make it ready for compilation.
Fixes#63520
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Minor updates both to make it more consistent with the
nrf53bsim documentation, and include more links
and a small section about the C library choice.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Update the documentation describing the bsim boards overall
to match the current reality.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add documentation for the newly introduced nrf5340bsim boards.
And rename the nrf52bsim documentation file as it is not the only
one anymore.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Minor updates as now we have also native_sim, so we
should not only refer to native_posix.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This reverts commit 8084ea55b7.
The rootcause is fixed in the ARC QEMU which is in SDK 0.16.3.
As we've updated SDK in upstream CI we can revert this
workaround.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Zephyr's code base uses MP_MAX_NUM_CPUS to
know how many cores exists in the target. It is
also expected that both symbols MP_MAX_NUM_CPUS
and MP_NUM_CPUS have the same value, so lets
just use MP_MAX_NUM_CPUS and simplify it.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Update flashing information for npcx7m6fb_evb and npcx9m6f_evb since
current OpenOCD in zephyr-sdk has supported them.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
While recent browsers seem to transparently try to use https when
hitting http://www.cypress.com/... URLs, they are effectively not
working anymore, so use https://www.cypress.com/... URLs instead. And
it's a good practice anyway to promote secure links vs. plain http :)
curl http://www.cypress.com/products/32-bit-arm-cortex-m4-psoc-6 -v -m 5
* Trying [2a02:26f0:2b00:1a::212:b1ac]:80...
* Connected to www.cypress.com (2a02:26f0:2b00:1a::212:b1ac) port 80
(#0)
> GET /products/32-bit-arm-cortex-m4-psoc-6 HTTP/1.1 Host:
> www.cypress.com User-Agent: curl/8.1.2 Accept: */*
>
* Operation timed out after 5004 milliseconds with 0 bytes received
* Closing connection 0 curl: (28) Operation timed out after 5004
milliseconds with 0 bytes received
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Support code coverage on all RISC-V qemu targets. Additional
boards may choose to enable coveage support as well.
Tested by following the procedure documented at
https://docs.zephyrproject.org/latest/develop/test/coverage.html
with the qemu_riscv64 target.
Signed-off-by: Christopher Friedt <cfriedt@meta.com>
This is the more useful document to point newer Zephyr users to.
The support documentation template is already mentioned in the guide
(under "Contributing your board"), but leave the existing link to it for
quick reference, just changing a few words.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Use clock control API to retrieve the counter module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This prepares support pwm capture APIs by extended current pwm
shim driver but use a differrence hal component:
- Introduce a Kconfig options that will be set when PWM pulse
generation API is used, it is also used to select the hal
component. Guarding current code inside this Kconfig option
- Increase #pwm-cells to 3, flags is supported for PWM capture
- Do not require duty-cycle and polarity be set in dt, PWM
capture doesn't need it.
- Rename emum value for pwm-mode to keep only key information
- Add preprocessor in case no channel is configured for generate
PWM output, to avoid warning when build
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
So it gets the command line arguments by default.
This eases running the BT test which run on the
nrf52_bsim.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Automatically start the Network domain CPU during HW boot.
In the real HW this CPU is held on reset until something else
(Typically the application MCU) releases it.
But doing so facilitates running tests in this MCU as there is
no requirement for an image for the application core.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
When we have more than 1 MCU, add the MCU number to the traces
so we can identify from which MCU they come from.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add options to force MCUs to boot/not boot, overriding
of how they would behave otherwise, as well as an
option to print info about the MCUs present in the
platform.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
As a development helper, add a kconfig option to
automatically start the MCU this Zephyr image is built
for during HW boot, even if in other circumstances
this MCU would not start automatically (for ex. because
another core is meant to release its reset).
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
As we will now we having more nrf5*_bsim boards defined in this
same folder, the old folder names became missleading.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
To allow knowing for which MCU are the options,
prepend them with the MCU number.
The primary/preferred MCU will also keep an alias to the
old options (without the cpu<n>_ prefix)
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Each MCU hooks need to be named according to its MCU number.
Rename the hooks appropriately.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
To be more accurate, as this option represents a microcontroller
number, not a CPU number.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Assign DMA channels/sources for all LPUARTs exist on the
board so that async APIs can be used for all instances
when enabled.
Because LPUART 1 & 9, LPUART 2 & 10 share the same DMA
sources for TX and RX, be aware when using async APIs
for those instances.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Updates Ethernet PHY devicetree bindings to be more consistent with
Linux by using the standard `reg` property for the PHY address instead
of a custom `address` property. As a result, MDIO controller bindings
now require standard `#address-cells` and `#size-cells` properties.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
Some Ethernet PHYs used the devicetree node name `phy`, while others
used `ethernet-phy`. Be consistent and use `ethernet-phy` throughout.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
* In Zephyr:
* The HW models now include N fake timers, and N
bst timers.
The embedded code needs to target the one for its
CPU specifically.
* Update the HW models module to
f4595802d32d103718bf50b3d390b7a450895843
Including the following:
* f459580 TEMP & ECB: Fix INTEN sideeffect prototypes
* 50c2abe nrfx_common: Fix build error with clang
* 5f0ae29 FICR: Add nrf53 variants
* 82ee9bd DPPI: On initialization, set all registers to their reset value
* 1472c34 NVMC & UICR: Readied for nrf53
* f425c08 NVMC & UICR: Refactor
* 3a4cfc2 RADIO: Parametrize ED_RSSIOFFS
* a20e9fc nrfx_get_irq_number() Add missing CCM peripheral for nrf5340net
* c199715 DPPI: Bugfix
* 93806ac Zephyr cmake: Align with nrf53 board rename
* 51f26a3 VREQCTRL: Add register stub and definitions for nrf53
* 802e0cf RADIO: Switch to level interrupts, readied for nrf53
* 49bcea2 Templates: Added shortcut check & event signaling version for s
* a880cd6 Template: Move static out of signal handler definition
* 709f82b TEMP: Switched to level interrupts, readied for nrf53
* 6ef0069 AES_CCM: Switched to level interrupts, readied for nrf53
* eaa89da RNG: Use common templates
* 75a6cb4 AAR: Switched to level interrupts, readied for nrf53
* fbf58f3 AES_ECB: Switched to level interrupts, readied for nrf53
* d084647 RNG: Bugfix in STOP subscription
* 8007318 Templates: Added template code for the most common models logic
* bab6a54 int ctrl: Added new API
* daaaaa0 config: Fix nrf53 Net core EGU instance HAL mapping
* 54570a0 nrf5340 RTC int mapping fix
* 043af26 nrfx_common: Provide nrfx_get_irq_number() for 5340 cores
* ecd7b9b SWI: Add SWI pseudo peripheral
* a70c73b CLOCK: Add missing TASK sideeffecting prototypes, and fix typo
* 56c7581 nrf5340: Split HAL files in net and app sets
* 3892d3e Add API to get the MCUs/domains names
* 8f485bc RADIO: Prevent clang build warning
* 5aac1c2 hal: Build weak version of the HAL for the 53 series also
* f18422d standalone nrfx_config: Provide needed definitions for nrf53
* 4015d5a nrfx_glue_bsim: Provide 2 trivial definitions for standalone bu
* 4af80d5 cmsis stubs: Provide trivial macro to replace ISB
* b6c2769 cmsis replacements: Fix for other Zephyr bsim targets
* 8316930 zephyr CMakefile: Set HAL version based on Kconfig
* 4404106 RNG: Rename functions to match new naming convention
* a3dbb38 RTC: Rename functions to match new naming convention
* 886dc73 CLOCK: Rename functions to match new naming convention
* bcb2b99 EGU: Rename functions to match new naming convention
* 50af67e TIMER: Rename functions to match new naming convention
* 8120224 CLOCK/POWER/RESET: Add DPPI connections, generalize to N instan
* 450337c RTC: Add DPPI connection, nrf53 support and new functionality
* 2918ce6 DPPI common subscription: Minor API change
* ec1c2a7 TIMER: Add DPPI connection, nrf53 support and functionality
* e6f9860 EGU: Add DPPI connection, nrf53 support and generalize
* c8a4368 bst_ticker: Generalize to N instances
* 093deee fake timer: Generalize to N instances
* 302da8d DPPI: Typo fix
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add a new kconfig option to be able to pass extra images to the
native simulator build.
So one can, for ex., use one application build to produce one core image,
and at the same time have it produce the final link with the native
simulator runner and the other MCU images.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The Zephyr build leaves all kconfig options as absolute symbols
in the image. This need to be localized, otherwise they will
appear as duplicates with other Zephyr images.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The platform is known for having unstable system timer with networking
enabled (see https://github.com/zephyrproject-rtos/zephyr/issues/48608)
causing occasional failures of time-sensitive networking testsuties
(TLS, now DHCPv6). Instead of excluding the platform on per-test basis,
just exclude the platform from networking testing globally.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Update the descriptions for the various CAN devicetree timing properties
specified in Time Quanta (TQ) to make it clear that these, if present, are
only used for the initial timing parameters.
Deprecate the (Re-)Synchronization Jump Width (SJW) devicetree properties
for both arbitration and data phase timing as these are now only used in
combination with the other TQ-based CAN timing properties, which are all
deprecated.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Adjust model names and compats for Intel alder-lake boards. Names are now
consistent with names used in other Intel boards.
Signed-off-by: Franciszek Zdobylak <fzdobylak@antmicro.com>
Add `mdio_read_c45()`/`mdio_write_c45()` APIs for Clause 45 access
and remove the `protocol` MDIO binding property so that MDIO bus
controller can support more than one protocol.
A new MDIO header is introduced with generic opcodes, MMD and
registers addresses, to be used by MDIO and PHY drivers.
Existing MDIO drivers that support both Clause 22 and Clause 45
access are migrated to the new APIs.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This renames the board from qemu_xtensa_dc233c to
qemu_xtensa_mmu to better signal that it is for testing with
MMU on QEMU Xtensa. Also turn on testing by default to make
sure future changes will not break Xtensa MMU support.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Set default value for LV_COLOR_16_SWAP when LVGL is enabled to get
correct colors out-of-the-box.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add 'hwinfo' to supported features list in CC1352* and CC26x2* based
boards yaml and documentation files. Driver for this platform was
included in 634416bc49.
Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
Adds into esp32s3_devkitm the appcpu board to allow
building applications running in ESP32S3 2nd core (appcpu).
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
While recent browsers seem to transparently try to use https for
http://www.st.com/... URLs, they are effectively not working anymore, so use
https://www.st.com/... URLs instead.
curl http://www.st.com/en/evaluation-tools/nucleo-g070rb.html -m 5 -v
* Trying 104.89.117.48:80...
* Connected to www.st.com (104.89.117.48) port 80 (#0)
> GET /en/evaluation-tools/nucleo-g070rb.html HTTP/1.1
> Host: www.st.com
> User-Agent: curl/8.1.2
> Accept: */*
>
* Operation timed out after 5002 milliseconds with 0 bytes received
* Closing connection 0
curl: (28) Operation timed out after 5002 milliseconds with 0 bytes
received
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
This code uses the `NRF_DT_GPIOS_TO_PSEL` macro, so it should include
`<soc.h>` explicitly and not rely on the header being included by some
other one.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The old CONFIG_UART_NS16550_ACCESS_IOPORT has been used to
indicate whether to access the NS16550 UART via IO port
before device tree is used to describe hardware. Now we have
device tree, and we can specify whether a particular UART
needs to be accessed via IO port using property io-mapped.
Therefore, CONFIG_UART_NS16550_ACCESS_IOPORT is no longer
needed (and thus also CONFIG_UART_NS16550_SIMULT_ACCESS).
Remove these two kconfigs and modify code to use device tree
to figure out how to access the UART hardware.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Prior to this patch, the BRD4170A did not enable the UART console
using pinctrl, which was recently added for this SoC series.
Signed-off-by: Warren Buffer <warren.buffer78@gmail.com>
This commit enables MSPI instance for apollo4p_blue_kxr_evb board.
Also adds pin configuration for each instance.
Signed-off-by: Aaron Ye <aye@ambiq.com>
This commit enables SPI instance for apollo4p_blue_kxr_evb board.
Also adds pin configuration for each instance.
Signed-off-by: Aaron Ye <aye@ambiq.com>
This commit enables I2C instance for apollo4p_blue_kxr_evb board.
Also adds pin configuration for each instance.
IOM4 is used for Bluetooth HCI-SPI inside of chip.
So no i2c4_default is defined.
Signed-off-by: Aaron Ye <aye@ambiq.com>
Update all Nucleo shield samples and references to them so that they
use the new zephyr:code-sample extension.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Set vendor to `snps` to be consistent with vendor in board yaml
file.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Add support for using SMARTDMA when using RM67162 display shield with
Zephyr, so that the DMA engine can be leveraged for improved performance
when using the MIPI DSI in command mode.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add multiple channels in overlay to test the sequencer.
Change clock source to correctly pass the test.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This is coming from devicetree and corrosponds to what we have in the
dts/bindings/vendor-prefixes.txt file.
This will allow for static filtering, especially with twister, i.e. no
need to build anything to know the vendor of a board
All of the vendor data was extracted automatically from the devicetree,
so some platforms might not have the right vendor or no vendor at all
right now, we need to fix some of the DTS information or do this
manually to get this 100% correct. But we are close.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Use clock control API to retrieve the module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Use clock control API to retrieve the module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Add support for npcx4m8f_evb board that is a development platform to
evaluate the Nuvoton NPCX4 embedded controller.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Use clock control API to retrieve the module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The native simulator final link can garbage collect unused
symbols. So let's ensure the symbol to keep ones are indeed
kept even if not used.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This migrates the subsys code samples to the new Sphinx code-sample
extension, making it easier to find relevant samples when browsing
API reference.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add node for VREF0 peripheral to LPC55S3X SOC DT
Clock VREF peripheral if status = okay in DT
Enable VREF on lpcxpresso55s36
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This patch updates the SPI flash to the one currently used in the
latest board version. Since these are still 0.X.X board versions,
old configurations are not explicitly supported.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
Demonstrate use of the Raspberry Pi Pico PIO SPI driver.
Added rpi_pico test cases to sample.yaml
Signed-off-by: Steve Boylan <stephen.boylan@beechwoods.com>
Just like for the nrf52_bsim let's add helper kconfig symbols
which can be used to identify we are running in a target that
is compatible with the real HW but is not the real HW.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Some SDK power macros are no longer available in the header
file. Add local defines in Zephyr.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Use the new code-sample directive and roles to document the networking
samples so that they show up as "Related samples" when browsing the
various relevant networking APIs.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Mark documents, which are included in other documents as :orphan:
following existing samples in Zephyr tree.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Add input codes to the gpio-keys devices, this makes the board build
correctly with the input samples, that are currently failing to build in
CI.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The RTC chip on i2c0 is a PCF8563, not a PCF8523.
RTC _almost_ works when using the latter, but not quite, hence why it
probably was missed before.
Fix tested as working using RTC Shell commands.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
This creates separate dtsi files for the various memory density codes of
SAM X2xfamilies (they are the same where the specific size exists.)
All of the boards with the exclusion of EV11L78A use the same density
model of 18 (32KiB RAM and 256KiB flash) which is what the samd2x.dtsi
include specified for all of them previously.
The density code has been confirmed being the same across the D20/D21,
C20/C21, L21, and R21 families. This does not carry over to some other
series such as the E5x.
Signed-off-by: Diego Elio Pettenò <flameeyes@meta.com>
Include the nrf peripheral kconfig definitions for all simulated
nrf boards, not just for the nrf52_bsim.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
ESP32C3 LuatOS core is a dev board with esp32-c3.
It has similar functions to esp32c3 devkitm, but smaller in size.
Signed-off-by: YuLong Yao <feilongphone@gmail.com>
This is the final step in making the `zephyr,memory-attr` property
actually useful.
The problem with the current implementation is that `zephyr,memory-attr`
is an enum type, this is making very difficult to use that to actually
describe the memory capabilities. The solution proposed in this PR is to
use the `zephyr,memory-attr` property as an OR-ed bitmask of memory
attributes.
With the change proposed in this PR it is possible in the DeviceTree to
mark the memory regions with a bitmask of attributes by using the
`zephyr,memory-attr` property. This property and the related memory
region can then be retrieved at run-time by leveraging a provided helper
library or the usual DT helpers.
The set of general attributes that can be specified in the property are
defined and explained in
`include/zephyr/dt-bindings/memory-attr/memory-attr.h` (the list can be
extended when needed).
For example, to mark a memory region in the DeviceTree as volatile,
non-cacheable, out-of-order:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_VOLATILE |
DT_MEM_NON_CACHEABLE |
DT_MEM_OOO )>;
};
The `zephyr,memory-attr` property can also be used to set
architecture-specific custom attributes that can be interpreted at run
time. This is leveraged, among other things, to create MPU regions out
of DeviceTree defined memory regions on ARM, for example:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-region = "NOCACHE_REGION";
zephyr,memory-attr = <( DT_ARM_MPU(ATTR_MPU_RAM_NOCACHE) )>;
};
See `include/zephyr/dt-bindings/memory-attr/memory-attr-mpu.h` to see
how an architecture can define its own special memory attributes (in
this case ARM MPU).
The property can also be used to set custom software-specific
attributes. For example we can think of marking a memory region as
available to be used for memory allocation (not yet implemented):
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_NON_CACHEABLE |
DT_MEM_SW_ALLOCATABLE )>;
};
Or maybe we can leverage the property to specify some alignment
requirements for the region:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_CACHEABLE |
DT_MEM_SW_ALIGN(32) )>;
};
The conventional and recommended way to deal and manage with memory
regions marked with attributes is by using the provided `mem-attr`
helper library by enabling `CONFIG_MEM_ATTR` (or by using the usual DT
helpers).
When this option is enabled the list of memory regions and their
attributes are compiled in a user-accessible array and a set of
functions is made available that can be used to query, probe and act on
regions and attributes, see `include/zephyr/mem_mgmt/mem_attr.h`
Note that the `zephyr,memory-attr` property is only a descriptive
property of the capabilities of the associated memory region, but it
does not result in any actual setting for the memory to be set. The
user, code or subsystem willing to use this information to do some work
(for example creating an MPU region out of the property) must use either
the provided `mem-attr` library or the usual DeviceTree helpers to
perform the required work / setting.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add yaml file for 'xen,xen', because without it an appropriate
'CONFIG_DT_HAS_XEN_XEN_ENABLED' isn't generated.
It will be used for checking Xen support on current setup, instead of
checking if it is BOARD/SOC "xenvm" (which is not correct for Domain-0
configurations).
Remove xen,xen-4.15.yaml at all, because it isn't necessary to have
yaml for some specific Xen version.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
Move memory mapping of Xen node to Grant Table driver system init
function. After moving mapping we don't need anymore records of
xen-xen node into 'mmu_regions' array, so they were deleted from
all SoCs: Rcar Gen3/Gen4 and XenVM.
We need at least 16M of virtual address space to map memory of Xen
node, so the virtual memory sized has been increased to 32 MB, it
should be enough for basic use-cases and mapping of 16M mem region
of Xen node.
Unfortunately, after moving we also need to increase number of XLAT
tables. The previous code was more efficient if we talking about
usage of XLAT tables, because it mapped grant tables using a higher-
order table that allows mapping blocks of 2MB. And after the changes
is maps every 4KB page, so we need more XLAT tables.
Increase number of grant frames, it is needed to sync stage 1 and stage 2
memory mappings, previously we map only one page on stage 2 and further
usage of unmap regions can cause MMU translation errors.
Perform mapping stage 1 before mapping for stage 2 (add to physmap),
because right after stage 1 we can try to access memory and if it is
unmap in stage 2, error will be received during translation.
Note: Xen Grant Table driver doesn't use Zephyr Device Model.
Authored-by: Mykola Kvach <mykola_kvach@epam.com>
Co-authored-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
