2ca6ffcd79
This is Intel's proprietary IP which supply the clock for all the system peripherals. Clock manager is initialized only one time during boot up by FSBL (ATF BL2) based on external user settings. Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
161 lines
4.5 KiB
C
161 lines
4.5 KiB
C
/*
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* Copyright (c) 2022-2023, Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_AGILEX5_LL_H_
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#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_AGILEX5_LL_H_
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#include <stdint.h>
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#include <zephyr/sys/sys_io.h>
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/* Clock manager register offsets */
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#define CLKMGR_CTRL 0x00
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#define CLKMGR_STAT 0x04
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#define CLKMGR_INTRCLR 0x14
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/* Clock manager main PLL group register offsets */
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#define CLKMGR_MAINPLL_OFFSET 0x24
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#define CLKMGR_MAINPLL_EN 0x00
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#define CLKMGR_MAINPLL_BYPASS 0x0C
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#define CLKMGR_MAINPLL_MPUCLK 0x18
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#define CLKMGR_MAINPLL_BYPASSS 0x10
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#define CLKMGR_MAINPLL_NOCCLK 0x1C
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#define CLKMGR_MAINPLL_NOCDIV 0x20
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#define CLKMGR_MAINPLL_PLLGLOB 0x24
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#define CLKMGR_MAINPLL_FDBCK 0x28
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#define CLKMGR_MAINPLL_MEM 0x2C
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#define CLKMGR_MAINPLL_MEMSTAT 0x30
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#define CLKMGR_MAINPLL_VCOCALIB 0x34
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#define CLKMGR_MAINPLL_PLLC0 0x38
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#define CLKMGR_MAINPLL_PLLC1 0x3C
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#define CLKMGR_MAINPLL_PLLC2 0x40
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#define CLKMGR_MAINPLL_PLLC3 0x44
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#define CLKMGR_MAINPLL_PLLM 0x48
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#define CLKMGR_MAINPLL_LOSTLOCK 0x54
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/* Clock manager peripheral PLL group register offsets */
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#define CLKMGR_PERPLL_OFFSET 0x7C
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#define CLKMGR_PERPLL_EN 0x00
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#define CLKMGR_PERPLL_BYPASS 0x0C
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#define CLKMGR_PERPLL_BYPASSS 0x10
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#define CLKMGR_PERPLL_EMACCTL 0x18
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#define CLKMGR_PERPLL_GPIODIV 0x1C
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#define CLKMGR_PERPLL_PLLGLOB 0x20
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#define CLKMGR_PERPLL_FDBCK 0x24
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#define CLKMGR_PERPLL_MEM 0x28
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#define CLKMGR_PERPLL_MEMSTAT 0x2C
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#define CLKMGR_PERPLL_VCOCALIB 0x30
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#define CLKMGR_PERPLL_PLLC0 0x34
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#define CLKMGR_PERPLL_PLLC1 0x38
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#define CLKMGR_PERPLL_PLLC2 0x3C
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#define CLKMGR_PERPLL_PLLC3 0x40
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#define CLKMGR_PERPLL_PLLM 0x44
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#define CLKMGR_PERPLL_LOSTLOCK 0x50
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/* Clock manager control/intel group register offsets */
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#define CLKMGR_INTEL_OFFSET 0xD0
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#define CLKMGR_INTEL_JTAG 0x00
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#define CLKMGR_INTEL_EMACACTR 0x4
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#define CLKMGR_INTEL_EMACBCTR 0x8
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#define CLKMGR_INTEL_EMACPTPCTR 0x0C
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#define CLKMGR_INTEL_GPIODBCTR 0x10
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#define CLKMGR_INTEL_SDMMCCTR 0x14
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#define CLKMGR_INTEL_S2FUSER0CTR 0x18
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#define CLKMGR_INTEL_S2FUSER1CTR 0x1C
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#define CLKMGR_INTEL_PSIREFCTR 0x20
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#define CLKMGR_INTEL_EXTCNTRST 0x24
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/* Clock manager macros */
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#define CLKMGR_CTRL_BOOTMODE_SET_MSK 0x00000001U
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#define CLKMGR_STAT_BUSY_E_BUSY 0x1
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#define CLKMGR_STAT_BUSY(x) (((x) & 0x00000001U) >> 0)
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#define CLKMGR_STAT_MAINPLLLOCKED(x) (((x) & 0x00000100U) >> 8)
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#define CLKMGR_STAT_PERPLLLOCKED(x) (((x) & 0x00010000U) >> 16)
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#define CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK 0x00000004U
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#define CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK 0x00000008U
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#define CLKMGR_MAINPLL_L4SPDIV(x) (((x) >> 16) & 0x3)
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#define CLKMGR_INTOSC_HZ 460000000U
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/* Shared Macros */
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#define CLKMGR_PSRC(x) (((x) & 0x00030000U) >> 16)
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#define CLKMGR_PSRC_MAIN 0
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#define CLKMGR_PSRC_PER 1
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#define CLKMGR_PLLGLOB_PSRC_EOSC1 0x0
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#define CLKMGR_PLLGLOB_PSRC_INTOSC 0x1
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#define CLKMGR_PLLGLOB_PSRC_F2S 0x2
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#define CLKMGR_PLLM_MDIV(x) ((x) & 0x000003FFU)
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#define CLKMGR_PLLGLOB_PD_SET_MSK 0x00000001U
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#define CLKMGR_PLLGLOB_RST_SET_MSK 0x00000002U
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#define CLKMGR_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003F00) >> 8)
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#define CLKMGR_PLLGLOB_AREFCLKDIV(x) (((x) & 0x00000F00) >> 8)
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#define CLKMGR_PLLGLOB_DREFCLKDIV(x) (((x) & 0x00003000) >> 12)
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#define CLKMGR_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003FF)
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#define CLKMGR_VCOCALIB_MSCNT_SET(x) (((x) << 16) & 0x00FF0000)
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#define CLKMGR_CLR_LOSTLOCK_BYPASS 0x20000000U
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#define CLKMGR_PLLC_DIV(x) ((x) & 0x7FF)
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#define CLKMGR_INTEL_SDMMC_CNT(x) (((x) & 0x7FF) + 1)
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/**
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* @brief Initialize the low layer clock control driver
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*
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* @param base_addr : Clock control device MMIO base address
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*
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* @return void
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*/
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void clock_agilex5_ll_init(mm_reg_t base_addr);
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/**
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* @brief Get MPU(Micro Processor Unit) clock value
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*
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* @param void
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*
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* @return returns MPU clock value
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*/
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uint32_t get_mpu_clk(void);
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/**
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* @brief Get Watchdog peripheral clock value
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*
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* @param void
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*
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* @return returns Watchdog clock value
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*/
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uint32_t get_wdt_clk(void);
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/**
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* @brief Get UART peripheral clock value
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*
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* @param void
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*
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* @return returns UART clock value
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*/
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uint32_t get_uart_clk(void);
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/**
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* @brief Get MMC peripheral clock value
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*
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* @param void
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*
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* @return returns MMC clock value
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*/
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uint32_t get_mmc_clk(void);
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/**
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* @brief Get Timer peripheral clock value
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*
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* @param void
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*
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* @return returns Timer clock value
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*/
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uint32_t get_timer_clk(void);
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#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_AGILEX5_LL_H_ */
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