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zephyr/soc/riscv
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Tyler Ng 432f4a0b9a soc/riscv/opentitan: Kconfig.defconfig.series: Set NUM_IRQS to 256 
The OpenTitan PLIC has support for up to 255 interrupt vectors, so
set it to that. Previously was set to number of IRQs used.

Signed-off-by: Tyler Ng <tkng@rivosinc.com>
2024-01-26 19:34:09 -06:00
..
andes_v5 linker: Generate snippets files for dtcm and itcm 2024-01-24 22:10:11 -06:00
common arch: riscv: make __soc_is_irq optional 2024-01-23 09:57:57 +01:00
efinix_sapphire soc: riscv: make RISCV_HAS_(C|P)LIC promptless 2024-01-23 09:57:57 +01:00
espressif_esp32 arch: riscv: make __soc_is_irq optional 2024-01-23 09:57:57 +01:00
gd_gd32 soc: riscv: make RISCV_HAS_(C|P)LIC promptless 2024-01-23 09:57:57 +01:00
intel_niosv soc: riscv: remove empty soc.h files 2024-01-19 15:13:53 +00:00
ite_ec it82xx2/usb: disable 15K-ohm default pull-down if device isn't enabled 2024-01-26 22:26:55 +00:00
litex_vexriscv soc: riscv: make RISCV_HAS_(C|P)LIC promptless 2024-01-23 09:57:57 +01:00
microchip_miv soc: riscv: make RISCV_HAS_(C|P)LIC promptless 2024-01-23 09:57:57 +01:00
neorv32 soc: riscv: riscv-privileged: drop soc_common.h 2024-01-15 09:58:03 +01:00
openisa_rv32m1 arch: riscv: make __soc_is_irq optional 2024-01-23 09:57:57 +01:00
opentitan soc/riscv/opentitan: Kconfig.defconfig.series: Set NUM_IRQS to 256 2024-01-26 19:34:09 -06:00
renode_virt soc: riscv: make RISCV_HAS_(C|P)LIC promptless 2024-01-23 09:57:57 +01:00
sifive_freedom soc: riscv: make RISCV_HAS_(C|P)LIC promptless 2024-01-23 09:57:57 +01:00
starfive_jh71xx soc: riscv: make RISCV_HAS_(C|P)LIC promptless 2024-01-23 09:57:57 +01:00
telink_tlsr soc: riscv: make RISCV_HAS_(C|P)LIC promptless 2024-01-23 09:57:57 +01:00
virt soc: riscv: make RISCV_HAS_(C|P)LIC promptless 2024-01-23 09:57:57 +01:00
CMakeLists.txt soc: riscv: move privileged code to common folder 2024-01-09 09:40:07 +01:00