Peter Marheine 1b931af0ff it8xxx2: fix build with CONFIG_SOC_IT8XXX2_PLL_FLASH_48M=n ... The chip I2C driver uses chip_get_pll_freq(), so that function needs to be built even when the PLL configuration is not changed at boot. Signed-off-by: Peter Marheine <pmarheine@chromium.org>		2022-10-21 20:31:47 +02:00
..
esp32c3	soc: riscv: esp32c3: include espressif's soc.h	2022-10-14 09:55:09 +02:00
litex-vexriscv	riscv: Introduce Zicsr and Zifencei extensions	2022-08-29 16:57:18 +02:00
openisa_rv32m1	intc: remove Kconfig.defconfig* setting of interrupt controller drivers	2022-09-01 10:25:36 +02:00
riscv-ite	it8xxx2: fix build with CONFIG_SOC_IT8XXX2_PLL_FLASH_48M=n	2022-10-21 20:31:47 +02:00
riscv-privilege	smp: Kconfig: Move to using MP_MAX_NUM_CPUS	2022-10-20 22:04:10 +09:00
CMakeLists.txt	riscv32: rename to riscv	2019-08-02 13:54:48 -07:00