28bb21cfe6
When a controller is running at full SDR speed at 12.5MHz, there needs to be enough time for the processor get around to writing more data in the fifo. Previously at -1 the size, this was enough for 1MHz with a decent processor, but not enough at a 12.5MHz SCL. Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com> |
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.. | ||
CMakeLists.txt | ||
i3c_ccc.c | ||
i3c_cdns.c | ||
i3c_common.c | ||
i3c_handlers.c | ||
i3c_ibi_workq.c | ||
i3c_mcux.c | ||
Kconfig | ||
Kconfig.cdns | ||
Kconfig.nxp |