Carlo Caione 3e92f11d1f riscv: Optimize t* registers usage ... In preparation for the support of RV32E optimize a bit the t* registers usage limiting that to t{0-2}. Signed-off-by: Carlo Caione <ccaione@baylibre.com>		2022-06-05 14:44:06 +02:00
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core	riscv: Optimize t* registers usage	2022-06-05 14:44:06 +02:00
include	arch: migrate includes to <zephyr/...>	2022-05-06 19:57:22 +02:00
CMakeLists.txt	riscv: toolchain arguments for a 64-bit build	2019-08-09 09:11:45 -05:00
Kconfig	riscv: Rework and cleanup Kconfig	2022-06-05 14:28:42 +02:00
Kconfig.core	riscv: Rework and cleanup Kconfig	2022-06-05 14:28:42 +02:00
Kconfig.isa	riscv: Rework and cleanup Kconfig	2022-06-05 14:28:42 +02:00