ca33905248
Driver implementation for the Xilinx Processor System MIO / EMIO GPIO controller as contained in the Zynq-7000 and ZynqMP (UltraScale) SoCs. The driver is split up into source and header for a parent controller device and source and header for 1..n child GPIO pin bank devices. The parent device driver takes care of IRQ handling, the GPIO pin bank driver provides pin / bank access according to the API defined by the GPIO subsystem. More than one device for this type of GPIO controller is required as it provides access to a number of GPIO pins well in excess of the 32 pins addressable by the current GPIO API (whereever parameters or return values come in the form of a bit mask): - Zynq-7000: 54 MIO GPIO pins, 64 EMIO GPIO pins in 4 banks. - ZynqMP: 78 MIO GPIO pins, 96 EMIO GPIO pins in 6 banks. Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
46 lines
1.2 KiB
C
46 lines
1.2 KiB
C
/*
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* Xilinx Processor System MIO / EMIO GPIO controller driver
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*
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* Driver private data declarations, parent (IRQ handler) module
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*
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* Copyright (c) 2022, Weidmueller Interface GmbH & Co. KG
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ZEPHYR_DRIVERS_GPIO_GPIO_XLNX_PS_H_
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#define _ZEPHYR_DRIVERS_GPIO_GPIO_XLNX_PS_H_
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/* Type definitions */
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/* IRQ handler function type */
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typedef void (*gpio_xlnx_ps_config_irq_t)(const struct device *dev);
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/**
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* @brief Run-time modifiable device data structure.
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*
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* This struct contains all data of the PS GPIO controller parent
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* (IRQ handler) which is modifiable at run-time.
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*/
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struct gpio_xlnx_ps_dev_data {
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struct gpio_driver_data common;
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};
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/**
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* @brief Constant device configuration data structure.
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*
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* This struct contains all data of the PS GPIO controller parent
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* which is required for proper operation (such as base memory
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* addresses, references to all associated banks etc.) which don't
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* have to and therefore cannot be modified at run-time.
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*/
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struct gpio_xlnx_ps_dev_cfg {
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struct gpio_driver_config common;
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uint32_t base_addr;
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const struct device **bank_devices;
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uint32_t num_banks;
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gpio_xlnx_ps_config_irq_t config_func;
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};
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#endif /* _ZEPHYR_DRIVERS_GPIO_GPIO_XLNX_PS_H_ */
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