Henrik Brix Andersen bc69500b0e drivers: can: stm32h7: fdcan: add support for domain clock and divider ... Add support for specifying the domain/kernel clock along with a common clock divider for the STM32H7 CAN controller driver via devicetree. Previously, the driver only supported using the PLL1_Q clock for domain/kernel clock, but now the driver defaults to the HSE clock, which is the chip default. Update existing boards to continue to use the PLL1_Q clock. Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>		2024-01-10 20:59:55 -05:00
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doc	doc: stm32: Update all st.com links to use HTTPS	2023-09-26 16:55:08 +02:00
arduino_portenta_h7-common.dtsi	drivers: can: stm32h7: fdcan: add support for domain clock and divider	2024-01-10 20:59:55 -05:00
arduino_portenta_h7_m4.dts
arduino_portenta_h7_m4.yaml	boards: add vendor to board yaml	2023-09-22 09:29:36 +02:00
arduino_portenta_h7_m4_defconfig
arduino_portenta_h7_m7.dts	drivers: regulator: fixed: simplify implementation	2022-11-30 15:49:30 +01:00
arduino_portenta_h7_m7.yaml	boards: add vendor to board yaml	2023-09-22 09:29:36 +02:00
arduino_portenta_h7_m7_defconfig
board.c	drivers: gpio: use gpio_is_ready_dt helper function	2023-08-28 08:48:35 -05:00
board.cmake
CMakeLists.txt
Kconfig.board
Kconfig.defconfig	soc: arm: st_stm32: Move STM32H7_DUAL_CORE	2023-04-24 13:30:46 +02:00