zephyr/arch/riscv
Katsuhiro Suzuki 4ce5f7ebe1 arch: riscv: fix hangup of multicore boot
This patch fixes hangup of RISC-V multicore boot.
Currently boot sequence uses a riscv_cpu_wake_flag to notify wakeup
request for secondary core(s).

But initial value of riscv_cpu_wake_flag is undefined, so current
mechanism is going to hangup if riscv_cpu_wake_flag and mhartid of
secondary core have the same value.

This is an example situation of this problem:

- hart1: check riscv_cpu_wake_flag (value is 1) and end the loop
- hart1: set riscv_cpu_wake_flag to 0
- hart0: set riscv_cpu_wake_flag to 1
         hart0 expects it will be changed to 0 by hart1 but it
         has never happened

Note:
  - hart0's mhartid is 0, hart1's mhartid is 1
  - hart0 is main, hart1 is secondary in this example

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2023-11-10 10:40:01 +01:00
..
core arch: riscv: fix hangup of multicore boot 2023-11-10 10:40:01 +01:00
include arch: riscv: add ARCH_HAS_SINGLE_THREAD_SUPPORT 2023-05-12 09:56:40 +02:00
CMakeLists.txt riscv: syscalls: use zephyr_syscall_header 2023-06-17 07:57:45 -04:00
Kconfig arch: riscv: Trap handler alignment configuration 2023-09-05 16:16:46 +02:00
Kconfig.core riscv: Introduce Zicsr and Zifencei extensions 2022-08-29 16:57:18 +02:00
Kconfig.isa riscv: Introduce BitManip extensions 2022-08-29 16:57:18 +02:00