Jaroslaw Stelter 9c0dd7e3be intel_adsp: ace20_lnl: Change LNL core count to 5 ... The ACE 2.0 LNL platform has 5 HIFI4 cores. Change number of cores to enable 5th core on the platform. Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>		2023-05-15 08:00:11 -04:00
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arc	ARC: Add HS4x support	2023-05-02 16:54:24 +02:00
arm	soc: stm32wl: Added logging declaration to soc.c	2023-05-15 09:59:22 +00:00
arm64	soc: Only select HAS_SEGGER_RTT if module is available	2023-04-20 14:57:51 +02:00
mips	asm: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
nios2	linker: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
posix	soc_inf: Refactor native tasks into own header	2023-04-13 13:35:20 +02:00
riscv	riscv: Microchip Mi-V should use built-in atomic operations	2023-05-09 13:04:27 +02:00
sparc	linker: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
x86	boards: rpl_crb: Indicate support for SMBus	2023-04-04 08:15:00 -04:00
xtensa	intel_adsp: ace20_lnl: Change LNL core count to 5	2023-05-15 08:00:11 -04:00
Kconfig	nrf52_bsim: Convert from a nRF52832 to a nRF52833	2023-01-26 09:29:18 +01:00