Khor Swee Aun 5b17a6da84 soc: riscv: riscv-privilege: INTEL NIOSV support ... Add support for INTEL FPGA NIOSV RISCV based Processors. Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com>		2023-02-20 09:29:13 -05:00
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esp32c3	driver: systimer: increase esp32c3 tick resolution	2023-01-04 14:24:25 +01:00
litex-vexriscv	riscv: Introduce Zicsr and Zifencei extensions	2022-08-29 16:57:18 +02:00
openisa_rv32m1	intc: remove Kconfig.defconfig* setting of interrupt controller drivers	2022-09-01 10:25:36 +02:00
riscv-ite	espi: it8xxx2: enable espi transaction interrupt	2023-01-18 09:55:44 +01:00
riscv-privilege	soc: riscv: riscv-privilege: INTEL NIOSV support	2023-02-20 09:29:13 -05:00
CMakeLists.txt	riscv32: rename to riscv	2019-08-02 13:54:48 -07:00