Gerard Marull-Paretas 68799d507d arch: riscv: make __soc_is_irq optional ... It looks like all SoCs in tree check if an exception comes from an IRQ the same way, so let's provide a common logic by default, still customizable if the SoC selects RISCV_SOC_ISR_CHECK. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>		2024-01-23 09:57:57 +01:00
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andes_v5	soc: riscv: make RISCV_HAS_(C|P)LIC promptless	2024-01-23 09:57:57 +01:00
common	arch: riscv: make __soc_is_irq optional	2024-01-23 09:57:57 +01:00
efinix_sapphire	soc: riscv: make RISCV_HAS_(C|P)LIC promptless	2024-01-23 09:57:57 +01:00
espressif_esp32	arch: riscv: make __soc_is_irq optional	2024-01-23 09:57:57 +01:00
gd_gd32	soc: riscv: make RISCV_HAS_(C|P)LIC promptless	2024-01-23 09:57:57 +01:00
intel_niosv	soc: riscv: remove empty soc.h files	2024-01-19 15:13:53 +00:00
ite_ec	arch: riscv: make __soc_is_irq optional	2024-01-23 09:57:57 +01:00
litex_vexriscv	soc: riscv: make RISCV_HAS_(C|P)LIC promptless	2024-01-23 09:57:57 +01:00
microchip_miv	soc: riscv: make RISCV_HAS_(C|P)LIC promptless	2024-01-23 09:57:57 +01:00
neorv32	soc: riscv: riscv-privileged: drop soc_common.h	2024-01-15 09:58:03 +01:00
openisa_rv32m1	arch: riscv: make __soc_is_irq optional	2024-01-23 09:57:57 +01:00
opentitan	soc: riscv: make RISCV_HAS_(C|P)LIC promptless	2024-01-23 09:57:57 +01:00
renode_virt	soc: riscv: make RISCV_HAS_(C|P)LIC promptless	2024-01-23 09:57:57 +01:00
sifive_freedom	soc: riscv: make RISCV_HAS_(C|P)LIC promptless	2024-01-23 09:57:57 +01:00
starfive_jh71xx	soc: riscv: make RISCV_HAS_(C|P)LIC promptless	2024-01-23 09:57:57 +01:00
telink_tlsr	soc: riscv: make RISCV_HAS_(C|P)LIC promptless	2024-01-23 09:57:57 +01:00
virt	soc: riscv: make RISCV_HAS_(C|P)LIC promptless	2024-01-23 09:57:57 +01:00
CMakeLists.txt	soc: riscv: move privileged code to common folder	2024-01-09 09:40:07 +01:00