a35848b7d7
Fix the interrupt setting in the fvp_baser_aemv8r dts: - The correct interrupt number is 5, not 0. - The interrupt priority and type are swapped. This patch also enables interrupt driven mode for this platform as this is the ideal setting for a Fast Models based platform. Issue-ID: SCM-4037 Signed-off-by: Filipe Rinaldi <filipe.rinaldi@arm.com> Change-Id: Ic4815f5afe4c9df9d8fe373d47d2773d64087c96 |
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| .. | ||
| bcm958402m2_a72 | ||
| fvp_base_revc_2xaemv8a | ||
| fvp_baser_aemv8r | ||
| intel_socfpga_agilex_socdk | ||
| nxp_ls1046ardb | ||
| qemu_cortex_a53 | ||
| xenvm | ||
| index.rst | ||