6b0b63b3a7
The finish interrupt after the previous transaction is completed may occur in the next transaction. To do hardware reset at this time could potentially lead to the failure of the transaction. Therefore, removing the hardware reset upon completing the transaction helps to avoid a race condition. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com> Signed-off-by: Dino Li <Dino.Li@ite.com.tw> |
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| .. | ||
| arc | ||
| arm | ||
| arm64 | ||
| common | ||
| mips | ||
| nios2 | ||
| posix | ||
| riscv | ||
| sparc | ||
| x86 | ||
| xtensa | ||
| CMakeLists.txt | ||
| Kconfig | ||