Tim Lin dca9cbff08 ITE: drivers/pinctrl: Add alternate function additional setting ... When the alternate setting is configured as func3, in addition to the setting of func3-gcr, some pins require external setting. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>		2023-09-25 09:48:57 +02:00
..
andes	dts/riscv: add missing riscv,isa fields and modify existing ones	2023-09-14 14:34:34 +02:00
efinix	dts/riscv: add missing riscv,isa fields and modify existing ones	2023-09-14 14:34:34 +02:00
espressif/esp32c3	dts/riscv: add missing riscv,isa fields and modify existing ones	2023-09-14 14:34:34 +02:00
gigadevice	dts/riscv: add missing riscv,isa fields and modify existing ones	2023-09-14 14:34:34 +02:00
ite	ITE: drivers/pinctrl: Add alternate function additional setting	2023-09-25 09:48:57 +02:00
lowrisc	dts/riscv: add missing riscv,isa fields and modify existing ones	2023-09-14 14:34:34 +02:00
microchip	dts/riscv: add missing riscv,isa fields and modify existing ones	2023-09-14 14:34:34 +02:00
niosv	dts: riscv: niosv: Fix status string	2023-09-19 15:23:36 +01:00
openisa	dts/riscv: add missing riscv,isa fields and modify existing ones	2023-09-14 14:34:34 +02:00
sifive	dts/riscv: add missing riscv,isa fields and modify existing ones	2023-09-14 14:34:34 +02:00
starfive	dts/riscv: add missing riscv,isa fields and modify existing ones	2023-09-14 14:34:34 +02:00
telink	riscv: telink_b91: fix compilation	2023-09-18 13:03:45 -04:00
neorv32.dtsi	dts/riscv: add missing riscv,isa fields and modify existing ones	2023-09-14 14:34:34 +02:00
riscv32-litex-vexriscv.dtsi	dts/riscv: add missing riscv,isa fields and modify existing ones	2023-09-14 14:34:34 +02:00
virt.dtsi	dts: riscv: virt: use sifive,clint0	2022-08-02 09:12:31 +02:00