Gerard Marull-Paretas 6edb0624d8 soc: riscv: gd32vf103: simplify MCAUSE exception mask handling ... The exception mask needs to cover MCAUSE bits 11:0, there's no need to overengineer this setting using DT properties. Ref. https://doc.nucleisys.com/nuclei_spec/isa/core_csr.html#mcause Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>		2024-01-15 09:58:03 +01:00
..
andes_v5	arch: riscv: drop RISCV_HAS_CPU_IDLE	2024-01-12 09:58:31 +01:00
common	soc: riscv: cleanup usage/definition of MCAUSE IRQ flag	2024-01-15 09:58:03 +01:00
efinix_sapphire	arch: riscv: drop RISCV_HAS_CPU_IDLE	2024-01-12 09:58:31 +01:00
espressif_esp32	soc: riscv: cleanup usage/definition of MCAUSE IRQ flag	2024-01-15 09:58:03 +01:00
gd_gd32	soc: riscv: gd32vf103: simplify MCAUSE exception mask handling	2024-01-15 09:58:03 +01:00
intel_niosv	arch: riscv: drop RISCV_HAS_CPU_IDLE	2024-01-12 09:58:31 +01:00
ite_ec	soc: riscv: cleanup usage/definition of MCAUSE IRQ flag	2024-01-15 09:58:03 +01:00
litex_vexriscv	arch: riscv: drop RISCV_HAS_CPU_IDLE	2024-01-12 09:58:31 +01:00
microchip_miv	arch: riscv: drop RISCV_HAS_CPU_IDLE	2024-01-12 09:58:31 +01:00
neorv32	arch: riscv: drop RISCV_HAS_CPU_IDLE	2024-01-12 09:58:31 +01:00
openisa_rv32m1	arch: riscv: define some RISC-V exception codes	2024-01-15 09:58:03 +01:00
opentitan	arch: riscv: drop RISCV_HAS_CPU_IDLE	2024-01-12 09:58:31 +01:00
renode_virt	arch: riscv: drop RISCV_HAS_CPU_IDLE	2024-01-12 09:58:31 +01:00
sifive_freedom	arch: riscv: drop RISCV_HAS_CPU_IDLE	2024-01-12 09:58:31 +01:00
starfive_jh71xx	arch: riscv: drop RISCV_HAS_CPU_IDLE	2024-01-12 09:58:31 +01:00
telink_tlsr	arch: riscv: drop RISCV_HAS_CPU_IDLE	2024-01-12 09:58:31 +01:00
virt	arch: riscv: drop RISCV_HAS_CPU_IDLE	2024-01-12 09:58:31 +01:00
CMakeLists.txt	soc: riscv: move privileged code to common folder	2024-01-09 09:40:07 +01:00