zephyr/arch/riscv
Mark Holden 7803a4e590 arch: riscv: ARCH_EXCEPT macro
Enable ARCH_EXCEPT macro for non-usermode scenario for RISC-V
Macro will now raise an illegal instruction exception so that mepc will
hold expected value in exception handler, and generated coredump can
reconstruct the failing stack

Coredump tests running on renode (for RISC-V) can now utilize fatal error
path through k_panic

Signed-off-by: Mark Holden <mholden@fb.com>
2022-01-01 07:38:20 -05:00
..
core arch: riscv: ARCH_EXCEPT macro 2022-01-01 07:38:20 -05:00
include kernel: mem_domain: arch_mem_domain functions to return errors 2021-11-22 12:45:22 -05:00
CMakeLists.txt riscv: toolchain arguments for a 64-bit build 2019-08-09 09:11:45 -05:00
Kconfig riscv: Add an option for configuring mcause exception mask 2021-12-20 17:51:30 +01:00