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riscv: Add an option for configuring mcause exception mask

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GD32V processor core is used non-standard bitmask
for mcause register. Add option to configure the bitmask
to support GD32V.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This commit is contained in:
TOKITA Hiroshi 2020-03-03 21:27:10 +09:00 committed by Carles Cufí
parent d79d4f0bea
commit 2de3133a05
2 changed files with 10 additions and 4 deletions
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7
arch/riscv/Kconfig
View file

@ -102,6 +102,13 @@ config RISCV_SOC_INTERRUPT_INIT
Enable SOC-based interrupt initialization
(call soc_interrupt_init, within _IntLibInit when enabled)
config RISCV_SOC_MCAUSE_EXCEPTION_MASK
hex
default 0x7FFFFFFFFFFFFFFF if 64BIT
default 0x7FFFFFFF
help
Specify the bits to use for exception code in mcause register.
config RISCV_GENERIC_TOOLCHAIN
bool "Compile using generic riscv32 toolchain"
default y

7
soc/riscv/riscv-privilege/common/soc_common.h
View file

@ -25,15 +25,14 @@
#ifdef CONFIG_64BIT
/* Interrupt Mask */
#define SOC_MCAUSE_IRQ_MASK (1 << 63)
/* Exception code Mask */
#define SOC_MCAUSE_EXP_MASK 0x7FFFFFFFFFFFFFFF
#else
/* Interrupt Mask */
#define SOC_MCAUSE_IRQ_MASK (1 << 31)
/* Exception code Mask */
#define SOC_MCAUSE_EXP_MASK 0x7FFFFFFF
#endif
/* Exception code Mask */
#define SOC_MCAUSE_EXP_MASK CONFIG_RISCV_SOC_MCAUSE_EXCEPTION_MASK
/* SOC-Specific EXIT ISR command */
#define SOC_ERET mret