41960ab366
Remove all optional, initial CAN sample point properties and rely on the CAN timing calculations to automatically pick the preferred sample point location based on the initial bitrate. Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
430 lines
10 KiB
Plaintext
430 lines
10 KiB
Plaintext
/*
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* Copyright (c) 2019 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <xtensa/xtensa.dtsi>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/clock/esp32_clock.h>
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#include <zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h>
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#include <dt-bindings/pinctrl/esp32-pinctrl.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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/ {
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chosen {
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zephyr,canbus = &twai;
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zephyr,entropy = &trng0;
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zephyr,flash-controller = &flash;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx6";
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reg = <0>;
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cpu-power-states = <&light_sleep &deep_sleep>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx6";
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reg = <1>;
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};
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power-states {
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light_sleep: light_sleep {
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compatible = "zephyr,power-state";
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power-state-name = "standby";
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min-residency-us = <200>;
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exit-latency-us = <60>;
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};
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deep_sleep: deep_sleep {
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compatible = "zephyr,power-state";
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power-state-name = "soft-off";
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min-residency-us = <2000>;
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exit-latency-us = <212>;
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};
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};
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};
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wifi: wifi {
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compatible = "espressif,esp32-wifi";
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status = "disabled";
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};
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eth: eth {
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compatible = "espressif,esp32-eth";
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interrupts = <ETH_MAC_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_EMAC_MODULE>;
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status = "disabled";
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};
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mdio: mdio {
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compatible = "espressif,esp32-mdio";
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clocks = <&rtc ESP32_EMAC_MODULE>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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pinctrl: pin-controller {
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compatible = "espressif,esp32-pinctrl";
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status = "okay";
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};
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soc {
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sram0: memory@3ffb0000 {
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compatible = "mmio-sram";
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reg = <0x3FFB0000 0x2c200>;
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};
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ipmmem0: memory@3ffe5230 {
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compatible = "mmio-sram";
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reg = <0x3FFE5230 0x400>;
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};
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shm0: memory@3ffe5630 {
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compatible = "mmio-sram";
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reg = <0x3FFE5630 0x3C00>;
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};
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intc: interrupt-controller@3ff00104 {
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#interrupt-cells = <1>;
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compatible = "espressif,esp32-intc";
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interrupt-controller;
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reg = <0x3ff00104 0x114>;
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status = "okay";
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};
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rtc: rtc@3ff48000 {
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compatible = "espressif,esp32-rtc";
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reg = <0x3ff48000 0x0D8>;
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xtal-freq = <ESP32_CLK_XTAL_40M>;
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#clock-cells = <1>;
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status = "okay";
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rtc_timer: rtc_timer {
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compatible = "espressif,esp32-rtc-timer";
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slow-clk-freq = <ESP32_RTC_SLOW_CLK_FREQ_150K>;
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interrupts = <RTC_CORE_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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status = "okay";
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};
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};
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flash: flash-controller@3ff42000 {
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compatible = "espressif,esp32-flash-controller";
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reg = <0x3ff42000 0x1000>;
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/* interrupts = <3 0>; */
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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erase-block-size = <4096>;
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write-block-size = <4>;
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/* Flash size is specified in SOC/SIP dtsi */
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};
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};
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psram0: psram@3f800000 {
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device_type = "memory";
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compatible = "mmio-sram";
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/* PSRAM size is specified in SOC/SIP dtsi */
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reg = <0x3f800000 DT_SIZE_M(2)>;
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status = "disabled";
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};
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ipm0: ipm@3ffed238 {
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compatible = "espressif,esp32-ipm";
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reg = <0x3FFED238 0x8>;
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status = "disabled";
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shared-memory = <&ipmmem0>;
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shared-memory-size = <0x400>;
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interrupts = <FROM_CPU_INTR0_SOURCE FROM_CPU_INTR1_SOURCE>;
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interrupt-parent = <&intc>;
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};
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ipi0: ipi@3f4c0058 {
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compatible = "espressif,crosscore-interrupt";
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reg = <0x3f4c0058 0x4>;
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interrupts = <FROM_CPU_INTR0_SOURCE>;
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interrupt-parent = <&intc>;
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};
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ipi1: ipi@3f4c005c {
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compatible = "espressif,crosscore-interrupt";
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reg = <0x3f4c005c 0x4>;
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interrupts = <FROM_CPU_INTR1_SOURCE>;
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interrupt-parent = <&intc>;
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};
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uart0: uart@3ff40000 {
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compatible = "espressif,esp32-uart";
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reg = <0x3ff40000 0x400>;
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interrupts = <UART0_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_UART0_MODULE>;
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status = "disabled";
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};
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uart1: uart@3ff50000 {
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compatible = "espressif,esp32-uart";
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reg = <0x3ff50000 0x400>;
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interrupts = <UART1_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_UART1_MODULE>;
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status = "disabled";
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};
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uart2: uart@3ff6e000 {
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compatible = "espressif,esp32-uart";
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reg = <0x3ff6E000 0x400>;
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interrupts = <UART2_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_UART2_MODULE>;
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status = "disabled";
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};
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pcnt: pcnt@3ff57000 {
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compatible = "espressif,esp32-pcnt";
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reg = <0x3ff57000 0x1000>;
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interrupts = <PCNT_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_PCNT_MODULE>;
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status = "disabled";
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};
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ledc0: ledc@3ff59000 {
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compatible = "espressif,esp32-ledc";
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#pwm-cells = <3>;
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reg = <0x3ff59000 0x800>;
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clocks = <&rtc ESP32_LEDC_MODULE>;
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status = "disabled";
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};
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mcpwm0: mcpwm@3ff5e000 {
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compatible = "espressif,esp32-mcpwm";
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reg = <0x3ff5e000 0x1000>;
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interrupts = <PWM0_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_PWM0_MODULE>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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mcpwm1: mcpwm@3ff6c000 {
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compatible = "espressif,esp32-mcpwm";
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reg = <0x3ff6c000 0x1000>;
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interrupts = <PWM1_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_PWM1_MODULE>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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gpio: gpio {
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compatible = "simple-bus";
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gpio-map-mask = <0xffffffe0 0xffffffc0>;
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gpio-map-pass-thru = <0x1f 0x3f>;
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gpio-map = <
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0x00 0x0 &gpio0 0x0 0x0
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0x20 0x0 &gpio1 0x0 0x0
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>;
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#gpio-cells = <2>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio0: gpio@3ff44000 {
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compatible = "espressif,esp32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x3ff44000 0x800>;
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interrupts = <GPIO_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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/* Maximum available pins (per port)
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* Actual occupied pins are specified
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* on part number dtsi level, using
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* the `gpio-reserved-ranges` property.
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*/
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ngpios = <32>; /* 0..31 */
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};
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gpio1: gpio@3ff44800 {
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compatible = "espressif,esp32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x3ff44800 0x800>;
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interrupts = <GPIO_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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ngpios = <8>; /* 32..39 */
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};
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};
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touch: touch@3ff48858 {
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compatible = "espressif,esp32-touch";
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reg = <0x3ff48858 0x38>;
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interrupts = <RTC_CORE_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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i2c0: i2c@3ff53000 {
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compatible = "espressif,esp32-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3ff53000 0x1000>;
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interrupts = <I2C_EXT0_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_I2C0_MODULE>;
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status = "disabled";
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};
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i2c1: i2c@3ff67000 {
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compatible = "espressif,esp32-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3ff67000 0x1000>;
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interrupts = <I2C_EXT1_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_I2C1_MODULE>;
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status = "disabled";
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};
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trng0: trng@3ff75144 {
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compatible = "espressif,esp32-trng";
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reg = <0x3FF75144 0x4>;
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/* interrupts = <33 0>; - FIXME: Enable interrupts when interrupt-controller got supported in device tree */
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status = "disabled";
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};
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wdt0: watchdog@3ff5f048 {
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compatible = "espressif,esp32-watchdog";
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reg = <0x3ff5f048 0x20>;
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interrupts = <TG0_WDT_LEVEL_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_TIMG0_MODULE>;
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status = "okay";
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};
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wdt1: watchdog@3ff60048 {
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compatible = "espressif,esp32-watchdog";
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reg = <0x3ff60048 0x20>;
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interrupts = <TG1_WDT_LEVEL_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_TIMG1_MODULE>;
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status = "disabled";
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};
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spi2: spi@3ff64000 {
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compatible = "espressif,esp32-spi";
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reg = <0x3ff64000 DT_SIZE_K(4)>;
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interrupts = <SPI2_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_HSPI_MODULE>;
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dma-clk = <ESP32_SPI_DMA_MODULE>;
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dma-host = <0>;
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status = "disabled";
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};
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spi3: spi@3ff65000 {
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compatible = "espressif,esp32-spi";
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reg = <0x3ff65000 DT_SIZE_K(4)>;
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interrupts = <SPI3_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_VSPI_MODULE>;
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dma-clk = <ESP32_SPI_DMA_MODULE>;
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dma-host = <1>;
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status = "disabled";
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};
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twai: can@3ff6b000 {
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compatible = "espressif,esp32-twai";
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reg = <0x3ff6b000 DT_SIZE_K(4)>;
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interrupts = <TWAI_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_TWAI_MODULE>;
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status = "disabled";
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};
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timer0: counter@3ff5f000 {
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compatible = "espressif,esp32-timer";
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reg = <0x3ff5f000 DT_SIZE_K(4)>;
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group = <0>;
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index = <0>;
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interrupts = <TG0_T0_LEVEL_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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timer1: counter@3ff5f024 {
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compatible = "espressif,esp32-timer";
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reg = <0x3ff5f024 DT_SIZE_K(4)>;
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group = <0>;
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index = <1>;
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interrupts = <TG0_T1_LEVEL_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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timer2: counter@3ff60000 {
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compatible = "espressif,esp32-timer";
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reg = <0x3ff60000 DT_SIZE_K(4)>;
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group = <1>;
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index = <0>;
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interrupts = <TG1_T0_LEVEL_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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timer3: counter@3ff60024 {
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compatible = "espressif,esp32-timer";
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reg = <0x3ff60024 DT_SIZE_K(4)>;
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group = <1>;
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index = <1>;
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interrupts = <TG1_T1_LEVEL_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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dac: dac@3ff48800 {
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compatible = "espressif,esp32-dac";
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reg = <0x3ff48800 0x100>;
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interrupts = <RTC_CORE_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_SARADC_MODULE>;
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#io-channel-cells = <1>;
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status = "disabled";
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};
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adc0: adc@3ff48800 {
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compatible = "espressif,esp32-adc";
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reg = <0x3ff48800 10>;
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unit = <1>;
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channel-count = <8>;
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#io-channel-cells = <1>;
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status = "disabled";
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};
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adc1: adc@3ff48890 {
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compatible = "espressif,esp32-adc";
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reg = <0x3ff48890 10>;
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unit = <2>;
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channel-count = <10>;
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#io-channel-cells = <1>;
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status = "disabled";
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};
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};
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};
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