zephyr/arch/x86
Daniel Leung 8cfdd91d54 x86: ia32/fatal: be explicit on pointer math with _df_tss.cr3
For some unknown reason, the pagetable address for _df_tss.cr3
did not get translated from virtual to physical. However,
the translation is done if the pointer to pagetable is obtained
through reference to the first array element (instead of simply
through the name of array). Without CR3 pointing to the page
table via physical address, double fault does not work. So
fixing this by being explicit with the page table pointer.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-03-03 20:10:22 -05:00
..
core x86: ia32/fatal: be explicit on pointer math with _df_tss.cr3 2021-03-03 20:10:22 -05:00
include kernel: add CONFIG_SRAM_OFFSET 2021-02-22 14:55:28 -05:00
zefi license: add missing SPDX headers 2021-02-11 08:05:16 -05:00
CMakeLists.txt timing: add support for x86 2020-09-05 13:28:38 -05:00
gen_gdt.py x86: gen_gdt: add address translation if needed 2021-03-03 20:10:22 -05:00
gen_idt.py x86: gen_idt.py: typo fix 2020-05-21 14:44:33 +02:00
gen_mmu.py x86: gen_mmu: also map SRAM if linking in virtual address space 2021-03-03 20:10:22 -05:00
ia32.cmake x86: add kconfigs and compiler flags for MMX and SSE* 2021-02-15 08:21:15 -05:00
intel64.cmake x86: add kconfigs and compiler flags for MMX and SSE* 2021-02-15 08:21:15 -05:00
Kconfig x86: use CONFIG_SRAM_OFFSET instead of CONFIG_X86_KERNEL_OFFSET 2021-02-22 14:55:28 -05:00
timing.c x86: use TSC for timing information 2021-01-22 11:05:30 -05:00