b38dab48c6
Use clock control API to retrieve the counter module's frequency and update the boards using it to provide the source clocks. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
101 lines
2.5 KiB
Plaintext
101 lines
2.5 KiB
Plaintext
/*
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* Copyright 2022-2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/nxp/nxp_s32z27x_r52.dtsi>
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/ {
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cpus {
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/delete-node/ cpu@4;
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/delete-node/ cpu@5;
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/delete-node/ cpu@6;
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/delete-node/ cpu@7;
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};
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soc {
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stm0: stm@76200000 {
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compatible = "nxp,s32-sys-timer";
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reg = <0x76200000 0x10000>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_RTU0_REG_INTF_CLK>;
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status = "disabled";
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};
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stm1: stm@76210000 {
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compatible = "nxp,s32-sys-timer";
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reg = <0x76210000 0x10000>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_RTU0_REG_INTF_CLK>;
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status = "disabled";
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};
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stm2: stm@76020000 {
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compatible = "nxp,s32-sys-timer";
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reg = <0x76020000 0x10000>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_RTU0_REG_INTF_CLK>;
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status = "disabled";
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};
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stm3: stm@76030000 {
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compatible = "nxp,s32-sys-timer";
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reg = <0x76030000 0x10000>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_RTU0_REG_INTF_CLK>;
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status = "disabled";
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};
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swt0: watchdog@76000000 {
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compatible = "nxp,s32-swt";
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reg = <0x76000000 0x10000>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_FIRC_CLK>;
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status = "disabled";
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};
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swt1: watchdog@76010000 {
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compatible = "nxp,s32-swt";
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reg = <0x76010000 0x10000>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_FIRC_CLK>;
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status = "disabled";
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};
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swt2: watchdog@76220000 {
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compatible = "nxp,s32-swt";
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reg = <0x76220000 0x10000>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_FIRC_CLK>;
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status = "disabled";
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};
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swt3: watchdog@76230000 {
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compatible = "nxp,s32-swt";
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reg = <0x76230000 0x10000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_FIRC_CLK>;
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status = "disabled";
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};
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swt4: watchdog@76140000 {
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compatible = "nxp,s32-swt";
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reg = <0x76140000 0x10000>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_FIRC_CLK>;
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status = "disabled";
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};
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pit0: pit@76150000 {
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compatible = "nxp,kinetis-pit";
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reg = <0x76150000 0x10000>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_P0_REG_INTF_CLK>;
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max-load-value = <0x00ffffff>;
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status = "disabled";
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};
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};
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};
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