Gerard Marull-Paretas 68799d507d arch: riscv: make __soc_is_irq optional ... It looks like all SoCs in tree check if an exception comes from an IRQ the same way, so let's provide a common logic by default, still customizable if the SoC selects RISCV_SOC_ISR_CHECK. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>		2024-01-23 09:57:57 +01:00
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CMakeLists.txt	cmake: riscv: update riscv SoC to use SOC_LINKER_SCRIPT variable	2023-11-03 11:01:23 +01:00
Kconfig	kconfig: Replace non-defconfig single-symbol 'if's with 'depends on'	2020-02-12 10:32:34 -06:00
Kconfig.defconfig	arch: riscv: use CONFIG_RISCV_MCAUSE_EXCEPTION_MASK	2024-01-15 09:58:03 +01:00
Kconfig.soc	riscv: Introduce Zicsr and Zifencei extensions	2022-08-29 16:57:18 +02:00
linker.ld	include: arch: arm: Remove aarch32 directory	2023-09-13 10:08:05 +01:00
pinctrl_soc.h	soc: riscv: openisa: rv32m1: add pinctrl header file	2022-05-05 13:34:39 -05:00
soc.c	soc: riscv: openisa_rv32m1: add missing includes	2024-01-19 15:13:53 +00:00
soc.h	arch: riscv: define local soc_interrupt_init prototypes	2024-01-15 09:58:03 +01:00
soc_context.h	arch: riscv: thread: Init soc context on stack	2020-07-13 15:00:19 -05:00
soc_irq.S	arch: riscv: make __soc_is_irq optional	2024-01-23 09:57:57 +01:00
soc_offsets.h	soc: riscv: openisa_rv32m1: add missing includes	2024-01-19 15:13:53 +00:00
soc_ri5cy.h	arch: riscv: use CONFIG_RISCV_MCAUSE_EXCEPTION_MASK	2024-01-15 09:58:03 +01:00
soc_zero_riscy.h	arch: riscv: use CONFIG_RISCV_MCAUSE_EXCEPTION_MASK	2024-01-15 09:58:03 +01:00
vector.S	riscv: Rename __irq_wrapper to _isr_wrapper	2022-06-21 20:27:20 -04:00
vector_table.ld	riscv: Rename __irq_wrapper to _isr_wrapper	2022-06-21 20:27:20 -04:00
wdog.S	asm: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00