452a2f67cd
Instead of custom SOC_MCAUSE_EXP_MASK definition. Note that SoCs selecting RISCV_PRIVILEGED already used such config indirectly (see changes in soc_common.h). Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
32 lines
969 B
C
32 lines
969 B
C
/*
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* Copyright (c) 2018 Foundries.io Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef SOC_RISCV32_OPENISA_RV32M1_SOC_ZERO_RISCY_H_
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#define SOC_RISCV32_OPENISA_RV32M1_SOC_ZERO_RISCY_H_
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/* Control and Status Registers (CSRs) available for ZERO_RISCY. */
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#define ZERO_RISCY_MSTATUS 0x300U
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#define ZERO_RISCY_MTVEC 0x305U
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#define ZERO_RISCY_MEPC 0x341U
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#define ZERO_RISCY_MCAUSE 0x342U
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#define ZERO_RISCY_PCCR0 0x780U
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#define ZERO_RISCY_PCCR1 0x781U
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#define ZERO_RISCY_PCCR2 0x782U
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#define ZERO_RISCY_PCCR3 0x783U
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#define ZERO_RISCY_PCCR4 0x784U
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#define ZERO_RISCY_PCCR5 0x785U
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#define ZERO_RISCY_PCCR6 0x786U
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#define ZERO_RISCY_PCCR7 0x787U
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#define ZERO_RISCY_PCCR8 0x788U
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#define ZERO_RISCY_PCCR9 0x789U
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#define ZERO_RISCY_PCCR10 0x78AU
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#define ZERO_RISCY_PCCR 0x78BU
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#define ZERO_RISCY_PCER 0x7A0U
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#define ZERO_RISCY_PCMR 0x7A1U
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#define ZERO_RISCY_MHARTID 0xF14U
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#endif /* SOC_RISCV32_OPENISA_RV32M1_SOC_ZERO_RISCY_H_ */
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