zephyr/arch/riscv
Lingutla Chandrasekhar 64aa25a8a4 RISCV: Support pm cpu ops for SMP
Add pm cpu ops to call the platform specific implementations for
bringing up secondary cores.

Signed-off-by: Lingutla Chandrasekhar <quic_lingutla@quicinc.com>
2023-10-23 11:36:01 +02:00
..
core RISCV: Support pm cpu ops for SMP 2023-10-23 11:36:01 +02:00
include arch: riscv: add ARCH_HAS_SINGLE_THREAD_SUPPORT 2023-05-12 09:56:40 +02:00
CMakeLists.txt riscv: syscalls: use zephyr_syscall_header 2023-06-17 07:57:45 -04:00
Kconfig arch: riscv: Trap handler alignment configuration 2023-09-05 16:16:46 +02:00
Kconfig.core riscv: Introduce Zicsr and Zifencei extensions 2022-08-29 16:57:18 +02:00
Kconfig.isa riscv: Introduce BitManip extensions 2022-08-29 16:57:18 +02:00