9c69368b1d
LL name for PLL1Q is not the same across STM32G0, STM32WL, STM32H5 and STM32H7 families. This allows to choose the proper definition depending on the family. Signed-off-by: Johan Lafon <johan.lafon@syslinbit.com>
108 lines
3.5 KiB
C
108 lines
3.5 KiB
C
/*
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* Copyright (c) 2017-2022 Linaro Limited.
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* Copyright (c) 2017 RnDity Sp. z o.o.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_CLOCK_CONTROL_CLOCK_STM32_LL_MCO_H_
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#define ZEPHYR_DRIVERS_CLOCK_CONTROL_CLOCK_STM32_LL_MCO_H_
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#include <stm32_ll_utils.h>
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#if CONFIG_CLOCK_STM32_MCO1_SRC_NOCLOCK
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#define MCO1_SOURCE LL_RCC_MCO1SOURCE_NOCLOCK
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#elif CONFIG_CLOCK_STM32_MCO1_SRC_EXT_HSE
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#define MCO1_SOURCE LL_RCC_MCO1SOURCE_EXT_HSE
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#elif CONFIG_CLOCK_STM32_MCO1_SRC_LSE
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#define MCO1_SOURCE LL_RCC_MCO1SOURCE_LSE
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#elif CONFIG_CLOCK_STM32_MCO1_SRC_HSE
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#define MCO1_SOURCE LL_RCC_MCO1SOURCE_HSE
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#elif CONFIG_CLOCK_STM32_MCO1_SRC_LSI
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#define MCO1_SOURCE LL_RCC_MCO1SOURCE_LSI
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#elif CONFIG_CLOCK_STM32_MCO1_SRC_MSI
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#define MCO1_SOURCE LL_RCC_MCO1SOURCE_MSI
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#elif CONFIG_CLOCK_STM32_MCO1_SRC_HSI
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#define MCO1_SOURCE LL_RCC_MCO1SOURCE_HSI
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#elif CONFIG_CLOCK_STM32_MCO1_SRC_HSI16
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#define MCO1_SOURCE LL_RCC_MCO1SOURCE_HSI
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#elif CONFIG_CLOCK_STM32_MCO1_SRC_HSI48
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#define MCO1_SOURCE LL_RCC_MCO1SOURCE_HSI48
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#elif CONFIG_CLOCK_STM32_MCO1_SRC_PLLCLK
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#define MCO1_SOURCE LL_RCC_MCO1SOURCE_PLLCLK
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#elif CONFIG_CLOCK_STM32_MCO1_SRC_PLLQCLK
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#if (CONFIG_SOC_SERIES_STM32G0X || CONFIG_SOC_SERIES_STM32WLX)
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#define MCO1_SOURCE LL_RCC_MCO1SOURCE_PLLQCLK
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#elif (CONFIG_SOC_SERIES_STM32H5X || CONFIG_SOC_SERIES_STM32H7X)
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#define MCO1_SOURCE LL_RCC_MCO1SOURCE_PLL1QCLK
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#else
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#error "PLLQCLK is not a valid clock source on your SOC"
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#endif
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#elif CONFIG_CLOCK_STM32_MCO1_SRC_PLLCLK_DIV2
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#define MCO1_SOURCE LL_RCC_MCO1SOURCE_PLLCLK_DIV_2
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#elif CONFIG_CLOCK_STM32_MCO1_SRC_PLL2CLK
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#define MCO1_SOURCE LL_RCC_MCO1SOURCE_PLL2CLK
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#elif CONFIG_CLOCK_STM32_MCO1_SRC_PLLI2SCLK
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#define MCO1_SOURCE LL_RCC_MCO1SOURCE_PLLI2SCLK
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#elif CONFIG_CLOCK_STM32_MCO1_SRC_PLLI2SCLK_DIV2
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#define MCO1_SOURCE LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2
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#elif CONFIG_CLOCK_STM32_MCO1_SRC_SYSCLK
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#define MCO1_SOURCE LL_RCC_MCO1SOURCE_SYSCLK
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#endif
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#if CONFIG_CLOCK_STM32_MCO2_SRC_SYSCLK
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#define MCO2_SOURCE LL_RCC_MCO2SOURCE_SYSCLK
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#elif CONFIG_CLOCK_STM32_MCO2_SRC_PLLI2S
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#define MCO2_SOURCE LL_RCC_MCO2SOURCE_PLLI2S
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#elif CONFIG_CLOCK_STM32_MCO2_SRC_HSE
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#define MCO2_SOURCE LL_RCC_MCO2SOURCE_HSE
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#elif CONFIG_CLOCK_STM32_MCO2_SRC_LSI
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#define MCO2_SOURCE LL_RCC_MCO2SOURCE_LSI
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#elif CONFIG_CLOCK_STM32_MCO2_SRC_CSI
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#define MCO2_SOURCE LL_RCC_MCO2SOURCE_CSI
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#elif CONFIG_CLOCK_STM32_MCO2_SRC_PLLCLK
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#define MCO2_SOURCE LL_RCC_MCO2SOURCE_PLLCLK
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#elif CONFIG_CLOCK_STM32_MCO2_SRC_PLLPCLK
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#define MCO2_SOURCE LL_RCC_MCO2SOURCE_PLL1PCLK
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#elif CONFIG_CLOCK_STM32_MCO2_SRC_PLL2PCLK
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#define MCO2_SOURCE LL_RCC_MCO2SOURCE_PLL2PCLK
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#endif
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#define fn_mco1_prescaler(v) LL_RCC_MCO1_DIV_ ## v
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#define mco1_prescaler(v) fn_mco1_prescaler(v)
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#define fn_mco2_prescaler(v) LL_RCC_MCO2_DIV_ ## v
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#define mco2_prescaler(v) fn_mco2_prescaler(v)
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* MCO configure doesn't active requested clock source,
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* so please make sure the clock source was enabled.
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*/
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__unused
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static inline void stm32_clock_control_mco_init(void)
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{
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#ifndef CONFIG_CLOCK_STM32_MCO1_SRC_NOCLOCK
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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LL_RCC_ConfigMCO(MCO1_SOURCE);
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#else
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LL_RCC_ConfigMCO(MCO1_SOURCE,
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mco1_prescaler(CONFIG_CLOCK_STM32_MCO1_DIV));
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#endif
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#endif /* CONFIG_CLOCK_STM32_MCO1_SRC_NOCLOCK */
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#ifndef CONFIG_CLOCK_STM32_MCO2_SRC_NOCLOCK
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LL_RCC_ConfigMCO(MCO2_SOURCE,
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mco2_prescaler(CONFIG_CLOCK_STM32_MCO2_DIV));
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#endif /* CONFIG_CLOCK_STM32_MCO2_SRC_NOCLOCK */
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_DRIVERS_CLOCK_CONTROL_CLOCK_STM32_LL_MCO_H_ */
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