zephyr/arch/riscv
Nicolas Pitre a211970b42 riscv: improve contended FPU switching
We can leverage the FPU dirty state as an indicator for preemptively
reloading the FPU content when a thread that did use the FPU before
being scheduled out is scheduled back in. This avoids the FPU access
trap overhead when switching between multiple threads with heavy FPU
usage.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2023-01-24 15:26:18 +01:00
..
core riscv: improve contended FPU switching 2023-01-24 15:26:18 +01:00
include riscv: integrate the new FPU context switching support 2023-01-24 15:26:18 +01:00
CMakeLists.txt riscv: toolchain arguments for a 64-bit build 2019-08-09 09:11:45 -05:00
Kconfig riscv: Allow SOC to override arch_irq_{lock,unlock,unlocked} 2023-01-09 19:21:39 +01:00
Kconfig.core riscv: Introduce Zicsr and Zifencei extensions 2022-08-29 16:57:18 +02:00
Kconfig.isa riscv: Introduce BitManip extensions 2022-08-29 16:57:18 +02:00