zephyr/dts/xtensa
Tomasz Leman a39a61015c dts: xtensa: intel: Reorder LNL power domains
This patch reorders the power domain definitions for the Intel ADSP ACE
2.0 LNL (Lunarlake) platform in the Device Tree Source (DTS).

Changes include:
- Removing the definitions for io2_domain, io3_domain, and ml1_domain,
  which are no longer present in the ACE 2.0 LNL configuration.
- Renaming and reassigning bit positions to existing power domains to
  reflect the updated power management architecture.

The reordering ensures that the DTS reflects the current power domain
architecture of the ACE 2.0 LNL platform, facilitating accurate power
management within the SoC.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2024-03-19 14:54:29 +01:00
..
espressif dts: bindings: can: remove optional sample point properties 2024-03-17 15:36:19 +01:00
intel dts: xtensa: intel: Reorder LNL power domains 2024-03-19 14:54:29 +01:00
nxp dts: xtensa: nxp_imx8: add EDMA0 node 2024-03-13 22:37:04 +00:00
dc233c.dtsi xtensa: dc233c: enlarge ROM space 2023-09-14 17:07:21 -04:00
sample_controller.dtsi dts: Add information about CPU frequency to the cpu nodes 2019-07-17 21:53:36 +02:00
xtensa.dtsi dts: Restructure xtensa dts directory 2019-06-27 07:21:11 -04:00