806c95163a
This commit adds/modifies `riscv,isa` strings using the following rules: * the ISA string is lowercase * multi-letter extensions are preceded with the underscore mark * if an extension is implied by another one, it is not specified - e.g. the D extension implies the F extension, so writing `rv32ifd` is redundant Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
14 lines
267 B
YAML
14 lines
267 B
YAML
# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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description: Espressif RISC-V CPU
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compatible: "espressif,riscv"
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include: riscv,cpus.yaml
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properties:
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clock-source:
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type: int
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description: cpu clock source
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