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zephyr/arch
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Gerard Marull-Paretas 0106e8d14c arch: riscv: introduce RISCV_PRIVILEGED 
Introduce a new arch level Kconfig option to signal the implementation
of the RISCV Privileged ISA spec. This replaces
SOC_FAMILY_RISCV_PRIVILEGED, because this is not a SoC specific
property, nor a SoC family.

Note that the SoC family naming scheme will be fixed in upcoming
commits.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-09 09:40:07 +01:00
..
arc style: fix misspelling in "precededs" 2023-12-20 11:55:46 +00:00
arm arm: debug: Add GDB stub for aarch32 2023-12-18 09:31:42 +01:00
arm64 arch: make CONFIG_EXCEPTION_DEBUG cross arch config 2023-12-14 09:32:27 +01:00
common arch: common: multilevel irq: verify interrupt level bits configuration 2023-12-08 08:40:41 -05:00
mips arch: mips: use LOG_ERR to print exceptions 2023-12-14 09:32:27 +01:00
nios2 arch: guard more code with CONFIG_EXCEPTION_DEBUG 2023-12-14 09:32:27 +01:00
posix native_simulator: Allow to pass extra options for localizing symbols 2023-12-06 09:25:41 +00:00
riscv arch: riscv: introduce RISCV_PRIVILEGED 2024-01-09 09:40:07 +01:00
sparc arch: guard more code with CONFIG_EXCEPTION_DEBUG 2023-12-14 09:32:27 +01:00
x86 x86: ia32/gdbstub: remove dead code 2024-01-08 20:54:16 -06:00
xtensa xtensa: mmu: invalidate mem domain TLBs during page table swap 2023-12-27 15:59:05 +00:00
CMakeLists.txt cmake: enable -Wshadow partially for in-tree code 2023-08-22 11:39:58 +02:00
Kconfig arch: make CONFIG_EXCEPTION_DEBUG cross arch config 2023-12-14 09:32:27 +01:00