zephyr/arch
Tomasz Bursztyka b1cc7312cf arch/x86: Fixing dcache enable/disable code
It did not build in x86_64 due to the fact that cr0 is a 64bits
register in such architecture, instead of being a 32bits one originaly
so the place holder has to follow that size. Such place holder must be
initialized to 0 to make sure no upper 32 bits ends up set which would
conclude in a general protection error.

Operand size specifier (l, q ...) is useless as well in this context.

Clearing up the masks by using proper macros.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2023-12-12 19:11:13 +01:00
..
arc arch: _PrepC -> z_prep_c 2023-12-11 18:23:52 -05:00
arm arch: arm: z_arm_prep_c -> z_prep_c 2023-12-11 18:23:52 -05:00
arm64 x86: add CODE_UNREACHABLE after z_cstart 2023-12-11 18:23:52 -05:00
common arch: common: multilevel irq: verify interrupt level bits configuration 2023-12-08 08:40:41 -05:00
mips arch: _PrepC -> z_prep_c 2023-12-11 18:23:52 -05:00
nios2 arch: _PrepC -> z_prep_c 2023-12-11 18:23:52 -05:00
posix native_simulator: Allow to pass extra options for localizing symbols 2023-12-06 09:25:41 +00:00
riscv arch: _PrepC -> z_prep_c 2023-12-11 18:23:52 -05:00
sparc arch: _PrepC -> z_prep_c 2023-12-11 18:23:52 -05:00
x86 arch/x86: Fixing dcache enable/disable code 2023-12-12 19:11:13 +01:00
xtensa xtensa: mmu: Fix tlb shootdown 2023-12-12 10:58:03 +01:00
CMakeLists.txt cmake: enable -Wshadow partially for in-tree code 2023-08-22 11:39:58 +02:00
Kconfig arch/Kconfig: Fix ARCH_POSIX comment 2023-12-07 10:39:31 +00:00