It did not build in x86_64 due to the fact that cr0 is a 64bits
register in such architecture, instead of being a 32bits one originaly
so the place holder has to follow that size. Such place holder must be
initialized to 0 to make sure no upper 32 bits ends up set which would
conclude in a general protection error.
Operand size specifier (l, q ...) is useless as well in this context.
Clearing up the masks by using proper macros.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Fix the way we read the current l1 page table set in the mmu.
We use it check if the current page table is different from the
running thread.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
We use ptevaddr_get to know the address the page table is set.
It happens that for this use, we should just use the ptebase field
of ptevaddr register.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The ring field in the pte mapping a memory partition should
be based in the partition attribute and not in the domain
asid that is used only to set the ASID (in RASID) position for
user ring.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The arm_core_tz.c trustzone driver was developed by Nordic and was
previously used by Nordic, but it is not used by us any more. Since we
stopped using it I can see that it has bit rotted (the include path
for tz.h is not available), so no else has started using it either
evidently.
Remove the broken and dead code.
We keep the HAS_ARM_SAU Kconfig as it is selected by a myriad of
platforms and determines if __SAUREGION_PRESENT is defined. I have
been unable to prove that this define is also unused.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Add `BUILD_ASSERT`s to make sure that the interrupt bits
allocated to each levels are enough to cover the number of
IRQs in each respective level.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Assert that the `local_irq` of each levels should only ranges
from `0` to `CONFIG_MAX_IRQ_PER_AGGREGATOR`, so that it doesn't
overflow the other aggregators.
Also, assert that the output of `z_get_sw_isr_table_idx` shouldn't
overflow the ISR table.
Update the `sw_isr_table` tests to test the range of
`CONFIG_MAX_IRQ_PER_AGGREGATOR` instead of the entire range of
level bits.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The `CAT_3RD_LVL_LIST` macro is only used when
`CONFIG_3RD_LEVEL_INTERRUPTS` is enabled, so move it into the
compiler guard.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The `irq` argument of the `Z_IF_DT_INTC_IRQN_EQ` macro
coincides with the `'irq'` argument passed into the `DT_IRQ`
macro, the former was supposed to be a number, while the latter
is a string/type, together this means that it was intepreted
as:
```c
DT_IRQ(node_id, <some_number>)
```
instead of
```c
DT_IRQ(node_id, irq)
```
as intended, so the macros never managed to match a device with
the IRQ properly, resulting in the `dev` member of the table
being NULL.
Solve this by renaming all the `irq` args in the macros to
`_irq` to avoid mixed usage.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The comment applies to all POSIX arch based targets,
not just native_posix.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add GDBSTUB_TRACE config option to extend GDB backend debug logging
for remote commands received and to debug the GDB stub itself.
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
Some libraries (like Openthread's spinel code) define their
API as externally linkable. This will make those symbols
remain as externally linkable by default after the
Zephyr build has produced the native simulator library
(MCU code).
When building an AMP native_simulator executable with
several MCUs each including these, the linker will see
those symbols as still linkable and duplicated, and
throw an error.
So let's give the option for users/developers of those
libraries to define extra symbols they want
to localize before assembling the final executable.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Remove old outdated include, causing build error. The acpi.h is not
needed since it is already included if ACPI is enabled and
INTEL_VTD_ICTL depends on ACPI.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Caches are optional on cortex-m7, having CPU_HAS_*CACHE in CPU_CORTEX_M7
definition renders them mandatory.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Use the returned reason from the secure fault handle function.
I see no reason why this was ignored, and it is used in the hardfault
handler.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Add support for relocating local symbols, as specified in the
.rela.dyn section.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
io_mapped seems to always exist even though it's not set anywhere, so
testing if it is different to 0 to actually define
UART_IS_IOPORT_ACCESS.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Most x86 build configurations enable the UART console. Since EFI console
has also defaulted to enabled, this means that the EFI covers the early
part of the boot until UART takes over.
This is all fine, except that enabling EFI console has the effect of
disabling PRINTK_SYNC. This in turn has the effect of causing garbled
output over UART, which has led to several bug reports on x86 platforms
(in particular on up_squared).
Since EFI console should really only be used for early platform bringup
and debugging purposes, it's not really ideal to unconditionally have it
enabled by default. Instead, change the default enabling to be
conditional to the UART console being disabled.
Fixes#54861Fixes#55071
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
introduce global DSP_SHARING and CPU_HAS_DSP to be used by all
architectures and change existing usage in ARC to use those global
configs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This PR fixes https://github.com/zephyrproject-rtos/zephyr/issues/64268
MWDT supposes .device_states section as BSS because .device_states
variables defined as uninitialized. This causes the section marked
as NOLOAD section and OpenOCD does not take it in account while
flashing it into board memory.
Finally .device_states variables becomes initialized with garbage
from RAM.
In this PR it's suggested to clean .device_states in early init stage.
Signed-off-by: Nikolay Agishev <agishev@synopsys.com>
This moves including of demand_paging.h out of kernel/mm.h,
so that users of demand paging APIs must include the header
explicitly. Since the main user is kernel itself, we can be
more discipline about header inclusion.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Remove limitation of enabling FP when building TF-M NS application.
FP support have been fixed in the tf-m-tests repository for NS
application.
Board support for NS executable may still be lacking for some boards.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Despite what the TF-M documentation says about SFN model not supporting
Floating Point, it does support it, according to TF-M developers.
Remove SFN limitation not supported with FP Hard ABI.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Annotate posix_exit() and nsi_exit() as noreturn
mainly to ease the life of static analysis tools.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Andy Ross re-implementation of MMU layer with some subtle changes,
like re-using existent macros, fix page table cache property when
direct mapping it in TLB.
From Andy's original commit message:
This is a reworked MMU layer, sitting cleanly below the page table
handling in the OS. Notable differences from the original work:
+ Significantly smaller code and simpler API (just three functions to
be called from the OS/userspace/ptable layer).
+ Big README-MMU document containing my learnings over the process, so
hopefully fewer people need to go through this in the future.
+ No TLB flushing needed. Clean separation of ASIDs, just requires
that the upper levels match the ASID to the L1 page table page
consistently.
+ Vector mapping is done with a 4k page and not a 4M page, leading to
much more flexibility with hardware memory layout. The original
scheme required that the 4M region containing vecbase be mapped
virtually to a location other than the hardware address, which makes
confusing linkage with call0 and difficult initialization
constraints where the exception vectors run at different addresses
before and after MMU setup (effectively forcing them to be PIC
code).
+ More provably correct initialization, all MMU changes happen in a
single asm block with no memory accesses which would generate a
refill.
Signed-off-by: Andy Ross <andyross@google.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This file doesn't need the asm2 header, and the preprocessor logic
around whether to include the backtrace header is needless (all it
does is declare functions).
Signed-off-by: Andy Ross <andyross@google.com>
Add a Kconfig option (and build warning) alerting about the problem
of the kernel spilling register in behave of the userspace.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Use thread local storage to check whether or not a thread is running
in user mode. This allows to use threadptr to properly support tls.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Only clear the user stack to 0xAA if CONFIG_INIT_STACKS is
enabled. Otherwise, write 0x00 as if the stack is in BSS.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
During arch_kernel_init(), the interrupt stack is being
initialized. However, if the current in-use stack is
the interrupt stack, it would wipe all the data up to
that point in stack, and might result in crash. So skip
initializing the interrupt stack if the current stack
pointer is within the boundary of interrupt stack.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
We need to use the mmu spin lock when invalidating the cache during
tlb shootdown, otherwise it is possible that this happens when another
thread is updating the page tables.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
When the target has a cache way size (cache size / cache wasy) bigger
than the page size we have cache aliasing, since the number of bits
required by the cache index is bigger than the number of bits in the page
offset.
To avoid this problem we flush the whole cache on context switch or when
the current page table is changed.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
