zephyr/boards/xtensa/intel_adsp_ace20_lnl
Anas Nashif e560bd6b8c boards: intel_adsp: fix board compatible
compatible was missing the hardware information.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-09-22 09:29:36 +02:00
..
board.cmake west: sign: add new west config [rimage].extra-args and a default key 2023-04-10 22:04:47 -04:00
intel_adsp_ace20_lnl.dts boards: intel_adsp: fix board compatible 2023-09-22 09:29:36 +02:00
intel_adsp_ace20_lnl.yaml boards: add vendor to board yaml 2023-09-22 09:29:36 +02:00
intel_adsp_ace20_lnl_defconfig boards: xtensa: Set DCACHE_LINE_SIZE for all SOF-supported Intel SoCs 2023-05-17 18:34:24 -04:00
Kconfig.board intel_adsp: ace20_lnl: add initial ace 2.0 (LNL) board definition 2023-04-03 15:17:21 +02:00
Kconfig.defconfig intel_adsp: ace20_lnl: add initial ace 2.0 (LNL) board definition 2023-04-03 15:17:21 +02:00