a3de3df5dc
Introduce new logic to set/release pm_constraint during serial TX transactions. First change is to introduce an internal flag and utility functions to control the set/release constraint balancing per uart device. This way, whatever the mix of transactions or API calls, we ensure a single uart device can only do 1 or 0 to the PM state constraint. Constraint can't then be set more than once, released w/o having been set or released more than it was set. The last part of the change reworks the triggers for constraints set/release operations. In order not to disturb driver operations, if irq driven mode or PM is enabled, don't enable TC interrupt handling by default. Instead, map the pm_constraint setting to the way TC flag is handled in normal mode of operations (irq driven or async). As a consequence, in irq driven mode, pm_constraint is set/released on tx_enable/tx_disable api calls, which gives API user full control on transaction protection vs low power operations. Finally, we emulate the same behavior on TX poll transaction, by enabling TC irq at the start of a stream and disabling TC irq once stream is completed. This is controlled with a dedicated device flag. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
82 lines
1.8 KiB
C
82 lines
1.8 KiB
C
/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief Driver for UART port on STM32 family processor.
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*
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*/
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#ifndef ZEPHYR_DRIVERS_SERIAL_UART_STM32_H_
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#define ZEPHYR_DRIVERS_SERIAL_UART_STM32_H_
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#include <drivers/pinmux.h>
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/* device config */
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struct uart_stm32_config {
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struct uart_device_config uconf;
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/* clock subsystem driving this peripheral */
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struct stm32_pclken pclken;
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/* initial hardware flow control, 1 for RTS/CTS */
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bool hw_flow_control;
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/* initial parity, 0 for none, 1 for odd, 2 for even */
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int parity;
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const struct soc_gpio_pinctrl *pinctrl_list;
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size_t pinctrl_list_size;
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#if defined(CONFIG_PM) \
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&& !defined(CONFIG_UART_INTERRUPT_DRIVEN) \
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&& !defined(CONFIG_UART_ASYNC_API)
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uart_irq_config_func_t irq_config_func;
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#endif
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};
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#ifdef CONFIG_UART_ASYNC_API
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struct uart_dma_stream {
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const struct device *dma_dev;
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uint32_t dma_channel;
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struct dma_config dma_cfg;
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uint8_t priority;
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bool src_addr_increment;
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bool dst_addr_increment;
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int fifo_threshold;
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struct dma_block_config blk_cfg;
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uint8_t *buffer;
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size_t buffer_length;
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size_t offset;
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volatile size_t counter;
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int32_t timeout;
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struct k_work_delayable timeout_work;
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bool enabled;
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};
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#endif
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/* driver data */
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struct uart_stm32_data {
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/* Baud rate */
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uint32_t baud_rate;
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/* clock device */
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const struct device *clock;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_callback_user_data_t user_cb;
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void *user_data;
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#endif
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#ifdef CONFIG_UART_ASYNC_API
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const struct device *uart_dev;
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uart_callback_t async_cb;
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void *async_user_data;
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struct uart_dma_stream dma_rx;
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struct uart_dma_stream dma_tx;
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uint8_t *rx_next_buffer;
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size_t rx_next_buffer_len;
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#endif
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#ifdef CONFIG_PM
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bool tx_poll_stream_on;
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bool pm_constraint_on;
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#endif
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};
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#endif /* ZEPHYR_DRIVERS_SERIAL_UART_STM32_H_ */
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