c880db1725
The CPU in Aspeed AST10x0 SOC is a ARM Cortex-M4 which doesn't internal cache memory. Aspeed implements an integrated system level cache to accelerate instruction and data memory accesses. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
21 lines
401 B
Plaintext
21 lines
401 B
Plaintext
# Copyright (c) 2021 Carlo Caione <ccaione@baylibre.com>
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# SPDX-License-Identifier: Apache-2.0
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menuconfig CACHE
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bool "External cache controllers drivers"
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help
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Enable support for external cache controllers drivers
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if CACHE
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module = CACHE
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module-str = cache
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source "subsys/logging/Kconfig.template.log_config"
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config CACHE_HAS_DRIVER
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bool
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endif # CACHE
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source "drivers/cache/Kconfig.aspeed"
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