zephyr/boards/arm64
Carlo Caione e4a125b6a4 dt: Make zephyr,memory-attr a capabilities bitmask
This is the final step in making the `zephyr,memory-attr` property
actually useful.

The problem with the current implementation is that `zephyr,memory-attr`
is an enum type, this is making very difficult to use that to actually
describe the memory capabilities. The solution proposed in this PR is to
use the `zephyr,memory-attr` property as an OR-ed bitmask of memory
attributes.

With the change proposed in this PR it is possible in the DeviceTree to
mark the memory regions with a bitmask of attributes by using the
`zephyr,memory-attr` property. This property and the related memory
region can then be retrieved at run-time by leveraging a provided helper
library or the usual DT helpers.

The set of general attributes that can be specified in the property are
defined and explained in
`include/zephyr/dt-bindings/memory-attr/memory-attr.h` (the list can be
extended when needed).

For example, to mark a memory region in the DeviceTree as volatile,
non-cacheable, out-of-order:

   mem: memory@10000000 {
       compatible = "mmio-sram";
       reg = <0x10000000 0x1000>;
       zephyr,memory-attr = <( DT_MEM_VOLATILE |
			       DT_MEM_NON_CACHEABLE |
			       DT_MEM_OOO )>;
   };

The `zephyr,memory-attr` property can also be used to set
architecture-specific custom attributes that can be interpreted at run
time. This is leveraged, among other things, to create MPU regions out
of DeviceTree defined memory regions on ARM, for example:

   mem: memory@10000000 {
       compatible = "mmio-sram";
       reg = <0x10000000 0x1000>;
       zephyr,memory-region = "NOCACHE_REGION";
       zephyr,memory-attr = <( DT_ARM_MPU(ATTR_MPU_RAM_NOCACHE) )>;
   };

See `include/zephyr/dt-bindings/memory-attr/memory-attr-mpu.h` to see
how an architecture can define its own special memory attributes (in
this case ARM MPU).

The property can also be used to set custom software-specific
attributes. For example we can think of marking a memory region as
available to be used for memory allocation (not yet implemented):

   mem: memory@10000000 {
       compatible = "mmio-sram";
       reg = <0x10000000 0x1000>;
       zephyr,memory-attr = <( DT_MEM_NON_CACHEABLE |
			       DT_MEM_SW_ALLOCATABLE )>;
   };

Or maybe we can leverage the property to specify some alignment
requirements for the region:

   mem: memory@10000000 {
       compatible = "mmio-sram";
       reg = <0x10000000 0x1000>;
       zephyr,memory-attr = <( DT_MEM_CACHEABLE |
			       DT_MEM_SW_ALIGN(32) )>;
   };

The conventional and recommended way to deal and manage with memory
regions marked with attributes is by using the provided `mem-attr`
helper library by enabling `CONFIG_MEM_ATTR` (or by using the usual DT
helpers).

When this option is enabled the list of memory regions and their
attributes are compiled in a user-accessible array and a set of
functions is made available that can be used to query, probe and act on
regions and attributes, see `include/zephyr/mem_mgmt/mem_attr.h`

Note that the `zephyr,memory-attr` property is only a descriptive
property of the capabilities of the associated memory  region, but it
does not result in any actual setting for the memory to be set. The
user, code or subsystem willing to use this information to do some work
(for example creating an MPU region out of the property) must use either
the provided `mem-attr` library or the usual DeviceTree helpers to
perform the required work / setting.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-09-15 12:46:54 +02:00
..
bcm958402m2_a72 dma: remove defconfig/proj setting of DMA drivers 2022-08-26 14:27:23 +00:00
fvp_base_revc_2xaemv8a samples: fully migrate basic samples to the new Sphinx extension 2023-09-13 09:15:34 +02:00
fvp_baser_aemv8r dt: Make zephyr,memory-attr a capabilities bitmask 2023-09-15 12:46:54 +02:00
intel_socfpga_agilex5_socdk boards: arm64: Add Intel SoC FPGA Agilex5 development kit board 2023-07-25 16:58:01 +00:00
intel_socfpga_agilex_socdk boards: arm64: intel_socfpga_agilex: Enable QSPI at agilex board 2022-09-01 14:30:59 -04:00
khadas_edgev boards: Add support for Khadas Edge-V board 2022-10-08 18:32:14 +02:00
mimx8mm_evk samples: fully migrate basic samples to the new Sphinx extension 2023-09-13 09:15:34 +02:00
mimx8mn_evk samples: fully migrate basic samples to the new Sphinx extension 2023-09-13 09:15:34 +02:00
mimx8mp_evk samples: fully migrate basic samples to the new Sphinx extension 2023-09-13 09:15:34 +02:00
mimx93_evk samples: fully migrate basic samples to the new Sphinx extension 2023-09-13 09:15:34 +02:00
nxp_ls1046ardb samples: fully migrate basic samples to the new Sphinx extension 2023-09-13 09:15:34 +02:00
phycore_am62x_a53 boards: arm64: phycore_am62x_a53: Update documentation 2023-05-12 14:18:53 +02:00
qemu_cortex_a53 samples: fully migrate basic samples to the new Sphinx extension 2023-09-13 09:15:34 +02:00
qemu_kvm_arm64 dts: qemu: a53: kvm: add DTS support for PCIe controller 2022-12-10 09:47:26 +01:00
rcar_h3ulcb_ca57 boards: rcar_h3ulcb_ca57: not a default platform 2023-08-30 06:39:39 -04:00
rcar_salvator_xs_m3 boards: arm64: add support of Salvator XS M3 board 2023-07-11 11:17:41 +02:00
xenvm dts: bindings: xen: add xen,xen.yaml file 2023-09-15 11:15:00 +01:00
index.rst boards: arm64: doc: only list index files 2021-04-27 13:31:42 -04:00