dc26d6bb4a
Most of the Renesas RCar Gen3 based SoC contains a Cortex R7 processor. This processor has access to the same memory mapped devices than the Cortex-A5x cores. - CPU operates upto 800MHz - Can use ram area from 0x40040000 to 0x42000000 - Has 512 interrupts on GIC-400 compliant with Arm GICv2 Add support for r8a77951 as first SoC of this series which is also known as H3 ES2.0 and is present present on different boards such as Salvator and R-Car Starter Kit(H3ulcb). This first SoC definition is just enough to print Hello World in a ram console. Signed-off-by: Julien Massot <julien.massot@iot.bzh> |
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| arc | ||
| arm | ||
| arm64 | ||
| nios2 | ||
| posix | ||
| riscv | ||
| sparc | ||
| x86 | ||
| xtensa | ||
| Kconfig | ||