| .. |
|
andes
|
drivers: intc: plic: set edge-triggered register address using compat
|
2023-12-08 07:51:05 -05:00 |
|
efinix
|
drivers: intc: plic: define all registers' offset in the driver
|
2023-10-04 09:06:28 -04:00 |
|
espressif/esp32c3
|
dts: bindings: can: deprecate the sjw and sjw-data properties
|
2023-09-28 16:28:56 +02:00 |
|
gd
|
soc: riscv: gd32vf103: simplify MCAUSE exception mask handling
|
2024-01-15 09:58:03 +01:00 |
|
ite
|
ITE: drivers/pinctrl: Distinguish between func3-gcr and func3-ext settings
|
2024-01-26 14:21:34 -05:00 |
|
lowrisc
|
drivers: intc: plic: define all registers' offset in the driver
|
2023-10-04 09:06:28 -04:00 |
|
microchip
|
dts: riscv: Fix a typo in riscv,isa for mpfs
|
2023-12-12 16:26:17 +01:00 |
|
niosv
|
dts: riscv: niosv: Fix status string
|
2023-09-19 15:23:36 +01:00 |
|
openisa
|
dts/riscv: add missing riscv,isa fields and modify existing ones
|
2023-09-14 14:34:34 +02:00 |
|
sifive
|
dts: riscv: sifive: fu540: add missing ngpios property
|
2024-01-19 15:13:53 +00:00 |
|
starfive
|
drivers: intc: plic: define all registers' offset in the driver
|
2023-10-04 09:06:28 -04:00 |
|
telink
|
drivers: intc: plic: define all registers' offset in the driver
|
2023-10-04 09:06:28 -04:00 |
|
neorv32.dtsi
|
dts/riscv: add missing riscv,isa fields and modify existing ones
|
2023-09-14 14:34:34 +02:00 |
|
renode_riscv32_virt.dtsi
|
dts: riscv: add a SoC dtsi for Renode RISC-V Virt SoC
|
2024-01-08 12:35:10 +01:00 |
|
riscv32-litex-vexriscv.dtsi
|
dts/riscv: add missing riscv,isa fields and modify existing ones
|
2023-09-14 14:34:34 +02:00 |
|
virt.dtsi
|
board: riscv: qemu: increase ndev of PLIC to 1024
|
2023-10-05 06:10:06 -04:00 |
a0a599b54b