zephyr/tests/arch/riscv/fpu_sharing/testcase.yaml

tests:
  arch.riscv.fpu_sharing:
    arch_allow: riscv
    filter: CONFIG_CPU_HAS_FPU
tests: riscv: test FPU sharing access behavior The RISC-V FPU context switching code is intricate and sometimes subtle. Here's a test that exercizes various code paths to ensure they work as intended, and to confirm that the target hardware does behave as expected too. Signed-off-by: Nicolas Pitre <npitre@baylibre.com> 2023-01-28 01:30:57 +01:00			`tests:`
			`arch.riscv.fpu_sharing:`
twister: s/riscv(32\|64)/riscv Only riscv is supported now, any 32/64-bit requirements need to use CONFIG_64BIT now. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com> 2024-02-07 11:26:32 +01:00			`arch_allow: riscv`
tests: riscv: test FPU sharing access behavior The RISC-V FPU context switching code is intricate and sometimes subtle. Here's a test that exercizes various code paths to ensure they work as intended, and to confirm that the target hardware does behave as expected too. Signed-off-by: Nicolas Pitre <npitre@baylibre.com> 2023-01-28 01:30:57 +01:00			`filter: CONFIG_CPU_HAS_FPU`