2015-05-20 18:40:39 +02:00
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# Kconfig - general architecture configuration options
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#
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# Copyright (c) 2014-2015 Wind River Systems, Inc.
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# Copyright (c) 2015 Intel Corporation
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2017-01-13 12:14:33 +01:00
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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2015-05-20 18:40:39 +02:00
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#
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2017-01-19 02:01:01 +01:00
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# SPDX-License-Identifier: Apache-2.0
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2015-05-20 18:40:39 +02:00
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#
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Kconfig: Use the first default with a satisfied condition
Up until now, Zephyr has patched Kconfig to use the last 'default' with
a satisfied condition, instead of the first one. I'm not sure why the
patch was added (it predates Kconfiglib), but I suspect it's related to
Kconfig.defconfig files.
There are at least three problems with the patch:
1. It's inconsistent with how Kconfig works in other projects, which
might confuse newcomers.
2. Due to oversights, earlier 'range' properties are still preferred,
as well as earlier 'default' properties on choices.
In addition to being inconsistent, this makes it impossible to
override 'range' properties and choice 'default' properties if the
base definition of the symbol/choice already has 'range'/'default'
properties.
I've seen errors caused by the inconsistency, and I suspect there
are more.
3. A fork of Kconfiglib that adds the patch needs to be maintained.
Get rid of the patch and go back to standard Kconfig behavior, as
follows:
1. Include the Kconfig.defconfig files first instead of last in
Kconfig.zephyr.
2. Include boards/Kconfig and arch/<arch>/Kconfig first instead of
last in arch/Kconfig.
3. Include arch/<arch>/soc/*/Kconfig first instead of last in
arch/<arch>/Kconfig.
4. Swap a few other 'source's to preserve behavior for some scattered
symbols with multiple definitions.
Swap 'source's in some no-op cases too, where it might match the
intent.
5. Reverse the defaults on symbol definitions that have more than one
default.
Skip defaults that are mutually exclusive, e.g. where each default
has an 'if <some board>' condition. They are already safe.
6. Remove the prefer-later-defaults patch from Kconfiglib.
Testing was done with a Python script that lists all Kconfig
symbols/choices with multiple defaults, along with a whitelist of fixed
symbols. The script also verifies that there are no "unreachable"
defaults hidden by defaults without conditions
As an additional test, zephyr/.config was generated before and after the
change for several samples and checked to be identical (after sorting).
This commit includes some default-related cleanups as well:
- Simplify some symbol definitions, e.g. where a default has 'if FOO'
when the symbol already has 'depends on FOO'.
- Remove some redundant 'default ""' for string symbols. This is the
implicit default.
Piggyback fixes for swapped ranges on BT_L2CAP_RX_MTU and
BT_L2CAP_TX_MTU (caused by confusing inconsistency).
Piggyback some fixes for style nits too, e.g. unindented help texts.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-07-30 10:57:47 +02:00
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# Include these first so that any properties (e.g. defaults) below can be
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# overriden (by defining symbols in multiple locations)
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2018-09-05 12:58:05 +02:00
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# Note: $ARCH might be a glob pattern
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2018-11-15 10:37:46 +01:00
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source "$(ARCH_DIR)/$(ARCH)/Kconfig"
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Kconfig: Use the first default with a satisfied condition
Up until now, Zephyr has patched Kconfig to use the last 'default' with
a satisfied condition, instead of the first one. I'm not sure why the
patch was added (it predates Kconfiglib), but I suspect it's related to
Kconfig.defconfig files.
There are at least three problems with the patch:
1. It's inconsistent with how Kconfig works in other projects, which
might confuse newcomers.
2. Due to oversights, earlier 'range' properties are still preferred,
as well as earlier 'default' properties on choices.
In addition to being inconsistent, this makes it impossible to
override 'range' properties and choice 'default' properties if the
base definition of the symbol/choice already has 'range'/'default'
properties.
I've seen errors caused by the inconsistency, and I suspect there
are more.
3. A fork of Kconfiglib that adds the patch needs to be maintained.
Get rid of the patch and go back to standard Kconfig behavior, as
follows:
1. Include the Kconfig.defconfig files first instead of last in
Kconfig.zephyr.
2. Include boards/Kconfig and arch/<arch>/Kconfig first instead of
last in arch/Kconfig.
3. Include arch/<arch>/soc/*/Kconfig first instead of last in
arch/<arch>/Kconfig.
4. Swap a few other 'source's to preserve behavior for some scattered
symbols with multiple definitions.
Swap 'source's in some no-op cases too, where it might match the
intent.
5. Reverse the defaults on symbol definitions that have more than one
default.
Skip defaults that are mutually exclusive, e.g. where each default
has an 'if <some board>' condition. They are already safe.
6. Remove the prefer-later-defaults patch from Kconfiglib.
Testing was done with a Python script that lists all Kconfig
symbols/choices with multiple defaults, along with a whitelist of fixed
symbols. The script also verifies that there are no "unreachable"
defaults hidden by defaults without conditions
As an additional test, zephyr/.config was generated before and after the
change for several samples and checked to be identical (after sorting).
This commit includes some default-related cleanups as well:
- Simplify some symbol definitions, e.g. where a default has 'if FOO'
when the symbol already has 'depends on FOO'.
- Remove some redundant 'default ""' for string symbols. This is the
implicit default.
Piggyback fixes for swapped ranges on BT_L2CAP_RX_MTU and
BT_L2CAP_TX_MTU (caused by confusing inconsistency).
Piggyback some fixes for style nits too, e.g. unindented help texts.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-07-30 10:57:47 +02:00
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2015-10-09 12:20:52 +02:00
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choice
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prompt "Architecture"
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default X86
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config ARC
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bool "ARC architecture"
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2018-03-15 01:16:40 +01:00
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select HAS_DTS
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2015-10-09 12:20:52 +02:00
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config ARM
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bool "ARM architecture"
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2017-12-05 15:07:39 +01:00
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select ARCH_HAS_THREAD_ABORT
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2018-11-03 13:19:18 +01:00
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select HAS_DTS
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2015-10-09 12:20:52 +02:00
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config X86
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bool "x86 architecture"
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2016-07-15 22:15:00 +02:00
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select ATOMIC_OPERATIONS_BUILTIN
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2018-11-03 13:19:18 +01:00
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select HAS_DTS
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2015-10-09 12:20:52 +02:00
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arch/x86_64: New architecture added
This patch adds a x86_64 architecture and qemu_x86_64 board to Zephyr.
Only the basic architecture support needed to run 64 bit code is
added; no drivers are added, though a low-level console exists and is
wired to printk().
The support is built on top of a "X86 underkernel" layer, which can be
built in isolation as a unit test on a Linux host.
Limitations:
+ Right now the SDK lacks an x86_64 toolchain. The build will fall
back to a host toolchain if it finds no cross compiler defined,
which is tested to work on gcc 8.2.1 right now.
+ No x87/SSE/AVX usage is allowed. This is a stronger limitation than
other architectures where the instructions work from one thread even
if the context switch code doesn't support it. We are passing
-no-sse to prevent gcc from automatically generating SSE
instructions for non-floating-point purposes, which has the side
effect of changing the ABI. Future work to handle the FPU registers
will need to be combined with an "application" ABI distinct from the
kernel one (or just to require USERSPACE).
+ Paging is enabled (it has to be in long mode), but is a 1:1 mapping
of all memory. No MMU/USERSPACE support yet.
+ We are building with -mno-red-zone for stack size reasons, but this
is a valuable optimization. Enabling it requires automatic stack
switching, which requires a TSS, which means it has to happen after
MMU support.
+ The OS runs in 64 bit mode, but for compatibility reasons is
compiled to the 32 bit "X32" ABI. So while the full 64 bit
registers and instruction set are available, C pointers are 32 bits
long and Zephyr is constrained to run in the bottom 4G of memory.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-08-19 21:24:48 +02:00
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config X86_64
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bool "x86_64 architecture"
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select ATOMIC_OPERATIONS_BUILTIN
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2019-02-20 01:03:39 +01:00
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select SCHED_IPI_SUPPORTED
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arch/x86_64: New architecture added
This patch adds a x86_64 architecture and qemu_x86_64 board to Zephyr.
Only the basic architecture support needed to run 64 bit code is
added; no drivers are added, though a low-level console exists and is
wired to printk().
The support is built on top of a "X86 underkernel" layer, which can be
built in isolation as a unit test on a Linux host.
Limitations:
+ Right now the SDK lacks an x86_64 toolchain. The build will fall
back to a host toolchain if it finds no cross compiler defined,
which is tested to work on gcc 8.2.1 right now.
+ No x87/SSE/AVX usage is allowed. This is a stronger limitation than
other architectures where the instructions work from one thread even
if the context switch code doesn't support it. We are passing
-no-sse to prevent gcc from automatically generating SSE
instructions for non-floating-point purposes, which has the side
effect of changing the ABI. Future work to handle the FPU registers
will need to be combined with an "application" ABI distinct from the
kernel one (or just to require USERSPACE).
+ Paging is enabled (it has to be in long mode), but is a 1:1 mapping
of all memory. No MMU/USERSPACE support yet.
+ We are building with -mno-red-zone for stack size reasons, but this
is a valuable optimization. Enabling it requires automatic stack
switching, which requires a TSS, which means it has to happen after
MMU support.
+ The OS runs in 64 bit mode, but for compatibility reasons is
compiled to the 32 bit "X32" ABI. So while the full 64 bit
registers and instruction set are available, C pointers are 32 bits
long and Zephyr is constrained to run in the bottom 4G of memory.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-08-19 21:24:48 +02:00
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2016-04-21 23:47:09 +02:00
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config NIOS2
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bool "Nios II Gen 2 architecture"
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2016-07-15 22:15:00 +02:00
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select ATOMIC_OPERATIONS_C
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2018-11-03 13:19:18 +01:00
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select HAS_DTS
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2016-04-21 23:47:09 +02:00
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arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
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config RISCV32
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bool "RISCV32 architecture"
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2018-11-02 19:29:59 +01:00
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select HAS_DTS
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arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
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2017-01-13 12:14:33 +01:00
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config XTENSA
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bool "Xtensa architecture"
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2019-02-01 14:52:05 +01:00
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select HAS_DTS
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2017-01-13 12:14:33 +01:00
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2017-10-03 16:31:55 +02:00
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config ARCH_POSIX
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bool "POSIX (native) architecture"
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select ATOMIC_OPERATIONS_BUILTIN
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select ARCH_HAS_CUSTOM_SWAP_TO_MAIN
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select ARCH_HAS_CUSTOM_BUSY_WAIT
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select ARCH_HAS_THREAD_ABORT
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select NATIVE_APPLICATION
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2019-02-03 13:04:17 +01:00
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select HAS_COVERAGE_SUPPORT
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2017-10-03 16:31:55 +02:00
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2015-10-09 12:20:52 +02:00
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endchoice
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2017-09-09 03:14:06 +02:00
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menu "General Architecture Options"
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2018-09-17 16:56:20 +02:00
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module = ARCH
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module-str = arch
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source "subsys/logging/Kconfig.template.log_config"
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module = MPU
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module-str = mpu
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source "subsys/logging/Kconfig.template.log_config"
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2018-10-09 11:59:16 +02:00
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config BIG_ENDIAN
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bool
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help
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This option tells the build system that the target system is
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big-endian. Little-endian architecture is the default and
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should leave this option unselected. This option is selected
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by arch/$ARCH/Kconfig, soc/**/Kconfig, or boards/**/Kconfig
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and the user should generally avoid modifying it. The option
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is used to select linker script OUTPUT_FORMAT and command
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line option for gen_isr_tables.py.
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2019-05-17 21:15:24 +02:00
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config 64BIT
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bool
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help
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This option tells the build system that the target system is
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using a 64-bit address space, meaning that pointer and long types
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are 64 bits wide. This option is selected by arch/$ARCH/Kconfig,
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soc/**/Kconfig, or boards/**/Kconfig and the user should generally
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avoid modifying it.
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2018-12-07 17:35:04 +01:00
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if ARC || ARM || NIOS2 || X86
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config SRAM_SIZE
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int "SRAM Size in kB"
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default $(dt_int_val,DT_SRAM_SIZE)
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help
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This option specifies the size of the SRAM in kB. It is normally set by
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the board's defconfig file and the user should generally avoid modifying
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it via the menu configuration.
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config SRAM_BASE_ADDRESS
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hex "SRAM Base Address"
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default $(dt_hex_val,DT_SRAM_BASE_ADDRESS)
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help
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This option specifies the base address of the SRAM on the board. It is
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normally set by the board's defconfig file and the user should generally
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avoid modifying it via the menu configuration.
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config FLASH_SIZE
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int "Flash Size in kB"
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default $(dt_int_val,DT_FLASH_SIZE) if (XIP && ARM) || !ARM
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help
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This option specifies the size of the flash in kB. It is normally set by
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the board's defconfig file and the user should generally avoid modifying
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it via the menu configuration.
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config FLASH_BASE_ADDRESS
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hex "Flash Base Address"
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default $(dt_hex_val,DT_FLASH_BASE_ADDRESS) if (XIP && ARM) || !ARM
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help
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2019-02-12 15:16:16 +01:00
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This option specifies the base address of the flash on the board. It is
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2018-12-07 17:35:04 +01:00
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normally set by the board's defconfig file and the user should generally
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avoid modifying it via the menu configuration.
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endif # ARM || ARC || NIOS2 || X86
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2018-10-12 09:27:28 +02:00
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if ARCH_HAS_TRUSTED_EXECUTION
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config TRUSTED_EXECUTION_SECURE
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bool "Trusted Execution: Secure firmware image"
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help
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Select this option to enable building a Secure firmware
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image for a platform that supports Trusted Execution. A
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Secure firmware image will execute in Secure state. It may
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allow the CPU to execute in Non-Secure (Normal) state.
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Therefore, a Secure firmware image shall be able to
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configure security attributions of CPU resources (memory
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areas, peripherals, interrupts, etc.) as well as to handle
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faults, related to security violations. It may optionally
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allow certain functions to be called from the Non-Secure
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(Normal) domain.
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config TRUSTED_EXECUTION_NONSECURE
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depends on !TRUSTED_EXECUTION_SECURE
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bool "Trusted Execution: Non-Secure firmware image"
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help
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Select this option to enable building a Non-Secure
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firmware image for a platform that supports Trusted
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Execution. A Non-Secure firmware image will execute
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in Non-Secure (Normal) state. Therefore, it shall not
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access CPU resources (memory areas, peripherals,
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interrupts etc.) belonging to the Secure domain.
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endif # ARCH_HAS_TRUSTED_EXECUTION
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2017-09-09 03:14:06 +02:00
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config HW_STACK_PROTECTION
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bool "Hardware Stack Protection"
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depends on ARCH_HAS_STACK_PROTECTION
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help
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2017-12-13 16:08:21 +01:00
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Select this option to enable hardware-based platform features to
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catch stack overflows when the system is running in privileged
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mode. If CONFIG_USERSPACE is not enabled, the system is always
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running in privileged mode.
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2017-11-06 20:42:54 +01:00
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2017-12-13 16:08:21 +01:00
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Note that this does not necessarily prevent corruption and assertions
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about the overall system state when a fault is triggered cannot be
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made.
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2017-09-09 03:14:06 +02:00
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2017-09-11 19:34:49 +02:00
|
|
|
config USERSPACE
|
2019-01-18 20:41:06 +01:00
|
|
|
bool "User mode threads"
|
2017-09-11 19:34:49 +02:00
|
|
|
depends on ARCH_HAS_USERSPACE
|
|
|
|
|
help
|
2017-12-13 16:08:21 +01:00
|
|
|
When enabled, threads may be created or dropped down to user mode,
|
|
|
|
|
which has significantly restricted permissions and must interact
|
|
|
|
|
with the kernel via system calls. See Zephyr documentation for more
|
|
|
|
|
details about this feature.
|
2017-09-11 19:34:49 +02:00
|
|
|
|
2017-12-13 16:08:21 +01:00
|
|
|
If a user thread overflows its stack, this will be caught and the
|
|
|
|
|
kernel itself will be shielded from harm. Enabling this option
|
|
|
|
|
may or may not catch stack overflows when the system is in
|
|
|
|
|
privileged mode or handling a system call; to ensure these are always
|
|
|
|
|
caught, enable CONFIG_HW_STACK_PROTECTION.
|
2017-11-06 20:42:54 +01:00
|
|
|
|
2018-02-01 08:19:49 +01:00
|
|
|
config PRIVILEGED_STACK_SIZE
|
|
|
|
|
int "Size of privileged stack"
|
2019-03-29 00:48:43 +01:00
|
|
|
default 1024
|
2018-02-01 08:19:49 +01:00
|
|
|
depends on ARCH_HAS_USERSPACE
|
|
|
|
|
help
|
2018-02-15 14:36:16 +01:00
|
|
|
This option sets the privileged stack region size that will be used
|
|
|
|
|
in addition to the user mode thread stack. During normal execution,
|
|
|
|
|
this region will be inaccessible from user mode. During system calls,
|
|
|
|
|
this region will be utilized by the system call.
|
2018-02-01 08:19:49 +01:00
|
|
|
|
2018-10-07 17:41:18 +02:00
|
|
|
config PRIVILEGED_STACK_TEXT_AREA
|
|
|
|
|
int "Privileged stacks text area"
|
2018-08-31 11:39:26 +02:00
|
|
|
default 512 if COVERAGE_GCOV
|
2019-02-20 23:49:36 +01:00
|
|
|
default 256
|
2018-10-07 17:41:18 +02:00
|
|
|
depends on ARCH_HAS_USERSPACE
|
|
|
|
|
help
|
|
|
|
|
Stack text area size for privileged stacks.
|
|
|
|
|
|
|
|
|
|
config KOBJECT_TEXT_AREA
|
|
|
|
|
int "Size if kobject text area"
|
2018-08-29 13:14:16 +02:00
|
|
|
default 512 if COVERAGE_GCOV
|
2019-03-15 10:54:06 +01:00
|
|
|
default 512 if NO_OPTIMIZATIONS
|
2019-02-20 23:49:36 +01:00
|
|
|
default 256
|
2018-10-07 17:41:18 +02:00
|
|
|
depends on ARCH_HAS_USERSPACE
|
|
|
|
|
help
|
|
|
|
|
Size of kernel object text area. Used in linker script.
|
|
|
|
|
|
2018-03-06 22:17:57 +01:00
|
|
|
config STACK_GROWS_UP
|
|
|
|
|
bool "Stack grows towards higher memory addresses"
|
|
|
|
|
help
|
|
|
|
|
Select this option if the architecture has upward growing thread
|
|
|
|
|
stacks. This is not common.
|
|
|
|
|
|
2017-09-11 19:34:49 +02:00
|
|
|
config MAX_THREAD_BYTES
|
|
|
|
|
int "Bytes to use when tracking object thread permissions"
|
|
|
|
|
default 2
|
|
|
|
|
depends on USERSPACE
|
|
|
|
|
help
|
2017-12-13 16:08:21 +01:00
|
|
|
Every kernel object will have an associated bitfield to store
|
|
|
|
|
thread permissions for that object. This controls the size of the
|
|
|
|
|
bitfield (in bytes) and imposes a limit on how many threads can
|
|
|
|
|
be created in the system.
|
2017-09-11 19:34:49 +02:00
|
|
|
|
2017-11-09 01:38:03 +01:00
|
|
|
config DYNAMIC_OBJECTS
|
2018-04-25 02:01:37 +02:00
|
|
|
bool "Allow kernel objects to be allocated at runtime"
|
2017-11-09 01:38:03 +01:00
|
|
|
depends on USERSPACE
|
|
|
|
|
help
|
|
|
|
|
Enabling this option allows for kernel objects to be requested from
|
2018-04-25 02:01:37 +02:00
|
|
|
the calling thread's resource pool, at a slight cost in performance
|
|
|
|
|
due to the supplemental run-time tables required to validate such
|
|
|
|
|
objects.
|
|
|
|
|
|
|
|
|
|
Objects allocated in this way can be freed with a supervisor-only
|
|
|
|
|
API call, or when the number of references to that object drops to
|
|
|
|
|
zero.
|
2017-11-09 01:38:03 +01:00
|
|
|
|
2017-09-09 14:40:43 +02:00
|
|
|
config SIMPLE_FATAL_ERROR_HANDLER
|
2018-08-14 16:19:20 +02:00
|
|
|
bool "Simple system fatal error handler"
|
2017-09-09 14:40:43 +02:00
|
|
|
default y if !MULTITHREADING
|
|
|
|
|
help
|
2017-12-13 16:08:21 +01:00
|
|
|
Provides an implementation of _SysFatalErrorHandler() that hard hangs
|
|
|
|
|
instead of aborting the faulting thread, and does not print anything,
|
|
|
|
|
for footprint-concerned systems. Only enable this option if you do not
|
|
|
|
|
want debug capabilities in case of system fatal error.
|
2017-09-09 14:40:43 +02:00
|
|
|
|
2018-11-07 23:40:43 +01:00
|
|
|
if ARCH_HAS_NOCACHE_MEMORY_SUPPORT
|
|
|
|
|
|
|
|
|
|
config NOCACHE_MEMORY
|
|
|
|
|
bool "Support for uncached memory"
|
|
|
|
|
help
|
|
|
|
|
Add a "nocache" read-write memory section that is configured to
|
|
|
|
|
not be cached. This memory section can be used to perform DMA
|
|
|
|
|
transfers when cache coherence issues are not optimal or can not
|
|
|
|
|
be solved using cache maintenance operations.
|
|
|
|
|
|
|
|
|
|
endif # ARCH_HAS_NOCACHE_MEMORY_SUPPORT
|
|
|
|
|
|
2017-09-09 14:39:38 +02:00
|
|
|
menu "Interrupt Configuration"
|
|
|
|
|
#
|
|
|
|
|
# Interrupt related configs
|
|
|
|
|
#
|
2018-10-31 00:53:56 +01:00
|
|
|
config DYNAMIC_INTERRUPTS
|
|
|
|
|
bool "Enable installation of IRQs at runtime"
|
|
|
|
|
help
|
|
|
|
|
Enable installation of interrupts at runtime, which will move some
|
|
|
|
|
interrupt-related data structures to RAM instead of ROM, and
|
|
|
|
|
on some architectures increase code size.
|
|
|
|
|
|
2017-09-09 14:39:38 +02:00
|
|
|
config GEN_ISR_TABLES
|
2018-08-14 16:19:20 +02:00
|
|
|
bool "Use generated IRQ tables"
|
2017-09-09 14:39:38 +02:00
|
|
|
help
|
2017-12-13 16:08:21 +01:00
|
|
|
This option controls whether a platform uses the gen_isr_tables
|
|
|
|
|
script to generate its interrupt tables. This mechanism will create
|
|
|
|
|
an appropriate hardware vector table and/or software IRQ table.
|
2017-09-09 14:39:38 +02:00
|
|
|
|
|
|
|
|
config GEN_IRQ_VECTOR_TABLE
|
2018-08-14 16:19:20 +02:00
|
|
|
bool "Generate an interrupt vector table"
|
2017-09-09 14:39:38 +02:00
|
|
|
default y
|
|
|
|
|
depends on GEN_ISR_TABLES
|
|
|
|
|
help
|
2017-12-13 16:08:21 +01:00
|
|
|
This option controls whether a platform using gen_isr_tables
|
|
|
|
|
needs an interrupt vector table created. Only disable this if the
|
|
|
|
|
platform does not use a vector table at all, or requires the vector
|
|
|
|
|
table to be in a format that is not an array of function pointers
|
|
|
|
|
indexed by IRQ line. In the latter case, the vector table must be
|
|
|
|
|
supplied by the application or architecture code.
|
2017-09-09 14:39:38 +02:00
|
|
|
|
|
|
|
|
config GEN_SW_ISR_TABLE
|
2018-08-14 16:19:20 +02:00
|
|
|
bool "Generate a software ISR table"
|
2017-09-09 14:39:38 +02:00
|
|
|
default y
|
|
|
|
|
depends on GEN_ISR_TABLES
|
|
|
|
|
help
|
2017-12-13 16:08:21 +01:00
|
|
|
This option controls whether a platform using gen_isr_tables
|
|
|
|
|
needs a software ISR table table created. This is an array of struct
|
|
|
|
|
_isr_table_entry containing the interrupt service routine and supplied
|
|
|
|
|
parameter.
|
2017-09-09 14:39:38 +02:00
|
|
|
|
|
|
|
|
config GEN_IRQ_START_VECTOR
|
|
|
|
|
int
|
|
|
|
|
default 0
|
|
|
|
|
depends on GEN_ISR_TABLES
|
|
|
|
|
help
|
2017-12-13 16:08:21 +01:00
|
|
|
On some architectures, part of the vector table may be reserved for
|
|
|
|
|
system exceptions and is declared separately from the tables
|
|
|
|
|
created by gen_isr_tables.py. When creating these tables, this value
|
|
|
|
|
will be subtracted from CONFIG_NUM_IRQS to properly size them.
|
|
|
|
|
This is a hidden option which needs to be set per architecture and
|
|
|
|
|
left alone.
|
2017-09-09 14:39:38 +02:00
|
|
|
|
2017-11-23 18:05:55 +01:00
|
|
|
|
|
|
|
|
config IRQ_OFFLOAD
|
|
|
|
|
bool "Enable IRQ offload"
|
|
|
|
|
help
|
|
|
|
|
Enable irq_offload() API which allows functions to be synchronously
|
|
|
|
|
run in interrupt context. Mainly useful for test cases.
|
|
|
|
|
|
2017-09-09 14:39:38 +02:00
|
|
|
endmenu # Interrupt configuration
|
|
|
|
|
|
2017-09-09 03:14:06 +02:00
|
|
|
endmenu
|
|
|
|
|
|
2017-09-09 14:39:38 +02:00
|
|
|
#
|
|
|
|
|
# Architecture Capabilities
|
|
|
|
|
#
|
2018-10-12 09:27:28 +02:00
|
|
|
config ARCH_HAS_TRUSTED_EXECUTION
|
|
|
|
|
bool
|
|
|
|
|
|
2017-09-09 03:14:06 +02:00
|
|
|
config ARCH_HAS_STACK_PROTECTION
|
|
|
|
|
bool
|
|
|
|
|
|
2017-09-11 19:34:49 +02:00
|
|
|
config ARCH_HAS_USERSPACE
|
|
|
|
|
bool
|
|
|
|
|
|
2017-10-18 02:01:48 +02:00
|
|
|
config ARCH_HAS_EXECUTABLE_PAGE_BIT
|
|
|
|
|
bool
|
|
|
|
|
|
2018-11-07 23:40:43 +01:00
|
|
|
config ARCH_HAS_NOCACHE_MEMORY_SUPPORT
|
|
|
|
|
bool
|
|
|
|
|
|
2019-02-10 11:05:51 +01:00
|
|
|
config ARCH_HAS_RAMFUNC_SUPPORT
|
|
|
|
|
bool
|
|
|
|
|
|
2017-12-05 15:07:39 +01:00
|
|
|
#
|
|
|
|
|
# Other architecture related options
|
|
|
|
|
#
|
|
|
|
|
|
|
|
|
|
config ARCH_HAS_THREAD_ABORT
|
|
|
|
|
bool
|
|
|
|
|
|
2016-03-19 00:43:40 +01:00
|
|
|
#
|
|
|
|
|
# Hidden PM feature configs which are to be selected by
|
|
|
|
|
# individual SoC.
|
|
|
|
|
#
|
2019-03-16 20:55:56 +01:00
|
|
|
config HAS_SYS_POWER_STATE_SLEEP_1
|
2018-09-18 08:18:37 +02:00
|
|
|
# Hidden
|
|
|
|
|
bool
|
|
|
|
|
help
|
2019-02-28 07:20:24 +01:00
|
|
|
This option signifies that the target supports the SYS_POWER_STATE_SLEEP_1
|
2018-09-18 08:18:37 +02:00
|
|
|
configuration option.
|
|
|
|
|
|
2019-03-16 20:55:56 +01:00
|
|
|
config HAS_SYS_POWER_STATE_SLEEP_2
|
2018-09-18 08:18:37 +02:00
|
|
|
# Hidden
|
|
|
|
|
bool
|
|
|
|
|
help
|
2019-02-28 07:20:24 +01:00
|
|
|
This option signifies that the target supports the SYS_POWER_STATE_SLEEP_2
|
2018-09-18 08:18:37 +02:00
|
|
|
configuration option.
|
|
|
|
|
|
2019-03-16 20:55:56 +01:00
|
|
|
config HAS_SYS_POWER_STATE_SLEEP_3
|
2016-03-19 00:43:40 +01:00
|
|
|
# Hidden
|
2016-05-25 01:17:13 +02:00
|
|
|
bool
|
|
|
|
|
help
|
2019-02-28 07:20:24 +01:00
|
|
|
This option signifies that the target supports the SYS_POWER_STATE_SLEEP_3
|
2017-12-13 16:08:21 +01:00
|
|
|
configuration option.
|
2016-11-10 08:16:27 +01:00
|
|
|
|
2019-03-16 20:55:56 +01:00
|
|
|
config HAS_SYS_POWER_STATE_DEEP_SLEEP_1
|
2018-09-18 08:18:37 +02:00
|
|
|
# Hidden
|
|
|
|
|
bool
|
|
|
|
|
help
|
|
|
|
|
This option signifies that the target supports the SYS_POWER_STATE_DEEP_SLEEP_1
|
|
|
|
|
configuration option.
|
|
|
|
|
|
2019-03-16 20:55:56 +01:00
|
|
|
config HAS_SYS_POWER_STATE_DEEP_SLEEP_2
|
2018-09-18 08:18:37 +02:00
|
|
|
# Hidden
|
|
|
|
|
bool
|
|
|
|
|
help
|
|
|
|
|
This option signifies that the target supports the SYS_POWER_STATE_DEEP_SLEEP_2
|
|
|
|
|
configuration option.
|
|
|
|
|
|
2019-03-16 20:55:56 +01:00
|
|
|
config HAS_SYS_POWER_STATE_DEEP_SLEEP_3
|
2019-02-04 15:30:57 +01:00
|
|
|
# Hidden
|
|
|
|
|
bool
|
|
|
|
|
help
|
|
|
|
|
This option signifies that the target supports the SYS_POWER_STATE_DEEP_SLEEP_3
|
|
|
|
|
configuration option.
|
|
|
|
|
|
2016-11-10 08:16:27 +01:00
|
|
|
config BOOTLOADER_CONTEXT_RESTORE_SUPPORTED
|
|
|
|
|
# Hidden
|
|
|
|
|
bool
|
|
|
|
|
help
|
2017-12-13 16:08:21 +01:00
|
|
|
This option signifies that the target has options of bootloaders
|
|
|
|
|
that support context restore upon resume from deep sleep
|
2016-11-10 08:16:27 +01:00
|
|
|
|
2017-11-23 23:43:54 +01:00
|
|
|
|
|
|
|
|
# End hidden CPU family configs
|
|
|
|
|
#
|
|
|
|
|
|
2018-10-12 09:27:28 +02:00
|
|
|
config CPU_HAS_TEE
|
|
|
|
|
bool
|
|
|
|
|
help
|
|
|
|
|
This option is enabled when the CPU has support for Trusted
|
|
|
|
|
Execution Environment (e.g. when it has a security attribution
|
|
|
|
|
unit).
|
|
|
|
|
|
2017-11-23 23:43:54 +01:00
|
|
|
config CPU_HAS_FPU
|
|
|
|
|
bool
|
|
|
|
|
help
|
|
|
|
|
This option is enabled when the CPU has hardware floating point
|
|
|
|
|
unit.
|
|
|
|
|
|
|
|
|
|
config CPU_HAS_MPU
|
|
|
|
|
bool
|
|
|
|
|
# Omit prompt to signify "hidden" option
|
|
|
|
|
help
|
|
|
|
|
This option is enabled when the CPU has a Memory Protection Unit (MPU).
|
|
|
|
|
|
2018-11-27 15:45:36 +01:00
|
|
|
config MEMORY_PROTECTION
|
|
|
|
|
bool
|
|
|
|
|
# Omit prompt to signify "hidden" option
|
|
|
|
|
help
|
|
|
|
|
This option is enabled when Memory Protection features are supported.
|
|
|
|
|
Memory protection support is currently available on ARC, ARM, and x86
|
|
|
|
|
architectures.
|
|
|
|
|
|
2018-02-01 08:12:32 +01:00
|
|
|
config MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT
|
|
|
|
|
bool
|
|
|
|
|
# Omit prompt to signify "hidden" option
|
|
|
|
|
help
|
2018-02-15 14:36:16 +01:00
|
|
|
This option is enabled when the MPU requires a power of two alignment
|
|
|
|
|
and size for MPU regions.
|
2018-02-01 08:12:32 +01:00
|
|
|
|
2018-09-25 14:05:56 +02:00
|
|
|
config MPU_REQUIRES_NON_OVERLAPPING_REGIONS
|
|
|
|
|
bool
|
|
|
|
|
# Omit prompt to signify "hidden" option
|
|
|
|
|
help
|
|
|
|
|
This option is enabled when the MPU requires the active (i.e. enabled)
|
|
|
|
|
MPU regions to be non-overlapping with each other.
|
2018-02-01 08:12:32 +01:00
|
|
|
|
2018-12-27 16:13:25 +01:00
|
|
|
menuconfig FLOAT
|
|
|
|
|
bool "Floating point"
|
|
|
|
|
depends on CPU_HAS_FPU
|
2019-05-09 21:57:57 +02:00
|
|
|
depends on ARM || X86
|
2017-11-23 23:43:54 +01:00
|
|
|
help
|
2017-12-13 16:08:21 +01:00
|
|
|
This option allows threads to use the floating point registers.
|
|
|
|
|
By default, only a single thread may use the registers.
|
2017-11-23 23:43:54 +01:00
|
|
|
|
2017-12-13 16:08:21 +01:00
|
|
|
Disabling this option means that any thread that uses a
|
|
|
|
|
floating point register will get a fatal exception.
|
2017-11-23 23:43:54 +01:00
|
|
|
|
2018-12-27 16:13:25 +01:00
|
|
|
if FLOAT
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|
2017-11-23 23:43:54 +01:00
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|
config FP_SHARING
|
2018-08-14 16:19:20 +02:00
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|
bool "Floating point register sharing"
|
2017-11-23 23:43:54 +01:00
|
|
|
help
|
2017-12-13 16:08:21 +01:00
|
|
|
This option allows multiple threads to use the floating point
|
|
|
|
|
registers.
|
2017-11-23 23:43:54 +01:00
|
|
|
|
2018-12-27 16:13:25 +01:00
|
|
|
endif # FLOAT
|
2017-11-23 23:43:54 +01:00
|
|
|
|
2016-03-19 00:43:40 +01:00
|
|
|
#
|
|
|
|
|
# End hidden PM feature configs
|
|
|
|
|
#
|
|
|
|
|
|
2015-10-09 12:20:52 +02:00
|
|
|
config ARCH
|
|
|
|
|
string
|
|
|
|
|
help
|
2017-12-13 16:08:21 +01:00
|
|
|
System architecture string.
|
2015-10-09 12:20:52 +02:00
|
|
|
|
|
|
|
|
config SOC
|
2016-03-31 14:07:42 +02:00
|
|
|
string
|
|
|
|
|
help
|
2018-09-03 22:44:13 +02:00
|
|
|
SoC name which can be found under soc/<arch>/<soc name>.
|
2017-12-13 16:08:21 +01:00
|
|
|
This option holds the directory name used by the build system to locate
|
2018-11-21 20:42:47 +01:00
|
|
|
the correct linker and header files for the SoC.
|
2016-03-31 14:07:42 +02:00
|
|
|
|
|
|
|
|
config SOC_SERIES
|
|
|
|
|
string
|
|
|
|
|
help
|
2018-09-03 22:44:13 +02:00
|
|
|
SoC series name which can be found under soc/<arch>/<family>/<series>.
|
2017-12-13 16:08:21 +01:00
|
|
|
This option holds the directory name used by the build system to locate
|
|
|
|
|
the correct linker and header files.
|
2016-03-31 14:07:42 +02:00
|
|
|
|
|
|
|
|
config SOC_FAMILY
|
|
|
|
|
string
|
|
|
|
|
help
|
2018-09-03 22:44:13 +02:00
|
|
|
SoC family name which can be found under soc/<arch>/<family>.
|
2017-12-13 16:08:21 +01:00
|
|
|
This option holds the directory name used by the build system to locate
|
|
|
|
|
the correct linker and header files.
|
2015-11-30 01:47:21 +01:00
|
|
|
|
2015-12-08 02:20:25 +01:00
|
|
|
config BOARD
|
|
|
|
|
string
|
|
|
|
|
help
|
2017-12-13 16:08:21 +01:00
|
|
|
This option holds the name of the board and is used to locate the files
|
|
|
|
|
related to the board in the source tree (under boards/).
|
|
|
|
|
The Board is the first location where we search for a linker.ld file,
|
|
|
|
|
if not found we look for the linker file in
|
2018-09-03 22:44:13 +02:00
|
|
|
soc/<arch>/<family>/<series>
|