2017-04-05 19:06:17 +02:00
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/*
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* Copyright (c) 2017, Christian Taedcke
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2019-12-09 15:46:24 +01:00
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* Copyright (c) 2020 Lemonbeat GmbH
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2017-04-05 19:06:17 +02:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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2022-05-06 10:25:46 +02:00
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#include <zephyr/drivers/uart.h>
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2022-10-12 02:30:15 +02:00
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#include <zephyr/irq.h>
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2017-04-05 19:06:17 +02:00
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#include <em_usart.h>
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#include <em_cmu.h>
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#include <soc.h>
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2022-09-07 10:57:12 +02:00
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#ifdef CONFIG_PINCTRL
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#include <zephyr/drivers/pinctrl.h>
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#else
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#include <em_gpio.h>
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#endif /* CONFIG_PINCTRL */
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2022-10-31 09:43:19 +01:00
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#if DT_NODE_HAS_PROP(id, peripheral_id)
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2019-09-20 08:34:57 +02:00
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#define USART_PREFIX cmuClock_USART
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#define UART_PREFIX cmuClock_UART
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2020-06-15 10:35:27 +02:00
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#define CLOCK_USART(id) _CONCAT(USART_PREFIX, id)
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#define CLOCK_UART(id) _CONCAT(UART_PREFIX, id)
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2022-10-31 09:43:19 +01:00
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#define GET_GECKO_USART_CLOCK(id) CLOCK_USART(DT_INST_PROP(id, peripheral_id))
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#define GET_GECKO_UART_CLOCK(id) CLOCK_UART(DT_INST_PROP(id, peripheral_id))
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#else
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2023-03-09 10:41:20 +01:00
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#if (USART_COUNT == 1)
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#define CLOCK_USART(ref) (((ref) == USART0) ? cmuClock_USART0 \
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: -1)
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#elif (USART_COUNT == 2)
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2022-10-31 09:43:19 +01:00
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#define CLOCK_USART(ref) (((ref) == USART0) ? cmuClock_USART0 \
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: ((ref) == USART1) ? cmuClock_USART1 \
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: -1)
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#elif (USART_COUNT == 3)
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#define CLOCK_USART(ref) (((ref) == USART0) ? cmuClock_USART0 \
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: ((ref) == USART1) ? cmuClock_USART1 \
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: ((ref) == USART2) ? cmuClock_USART2 \
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: -1)
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#elif (USART_COUNT == 4)
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#define CLOCK_USART(ref) (((ref) == USART0) ? cmuClock_USART0 \
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: ((ref) == USART1) ? cmuClock_USART1 \
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: ((ref) == USART2) ? cmuClock_USART2 \
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: ((ref) == USART3) ? cmuClock_USART3 \
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: -1)
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#elif (USART_COUNT == 5)
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#define CLOCK_USART(ref) (((ref) == USART0) ? cmuClock_USART0 \
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: ((ref) == USART1) ? cmuClock_USART1 \
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: ((ref) == USART2) ? cmuClock_USART2 \
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: ((ref) == USART3) ? cmuClock_USART3 \
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: ((ref) == USART4) ? cmuClock_USART4 \
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: -1)
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#elif (USART_COUNT == 6)
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#define CLOCK_USART(ref) (((ref) == USART0) ? cmuClock_USART0 \
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: ((ref) == USART1) ? cmuClock_USART1 \
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: ((ref) == USART2) ? cmuClock_USART2 \
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: ((ref) == USART3) ? cmuClock_USART3 \
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: ((ref) == USART4) ? cmuClock_USART4 \
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: ((ref) == USART5) ? cmuClock_USART5 \
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: -1)
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#else
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#error "Undefined number of USARTs."
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#endif /* USART_COUNT */
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#define CLOCK_UART(ref) (((ref) == UART0) ? cmuClock_UART0 \
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: ((ref) == UART1) ? cmuClock_UART1 \
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: -1)
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#define GET_GECKO_USART_CLOCK(id) CLOCK_USART((USART_TypeDef *)DT_INST_REG_ADDR(id))
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#define GET_GECKO_UART_CLOCK(id) CLOCK_UART((USART_TypeDef *)DT_INST_REG_ADDR(id))
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#endif /* DT_NODE_HAS_PROP(id, peripheral_id) */
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2019-09-20 08:34:57 +02:00
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2019-12-09 15:46:24 +01:00
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/* Helper define to determine if SOC supports hardware flow control */
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2022-09-07 10:57:12 +02:00
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#if ((_SILICON_LABS_32B_SERIES > 0) || \
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(defined(_USART_ROUTEPEN_RTSPEN_MASK) && \
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2019-12-09 15:46:24 +01:00
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defined(_USART_ROUTEPEN_CTSPEN_MASK)))
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#define HW_FLOWCONTROL_IS_SUPPORTED_BY_SOC
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#endif
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#define HAS_HFC_OR(inst) DT_INST_PROP(inst, hw_flow_control) ||
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#define DT_DRV_COMPAT silabs_gecko_uart
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/* Has any enabled uart instance hw-flow-control enabled? */
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2022-09-07 10:57:12 +02:00
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#define UART_GECKO_UART_HW_FLOW_CONTROL_ENABLED \
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2019-12-09 15:46:24 +01:00
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DT_INST_FOREACH_STATUS_OKAY(HAS_HFC_OR) 0
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#undef DT_DRV_COMPAT
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#define DT_DRV_COMPAT silabs_gecko_usart
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/* Has any enabled usart instance hw-flow-control enabled? */
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2022-09-07 10:57:12 +02:00
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#define UART_GECKO_USART_HW_FLOW_CONTROL_ENABLED \
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2019-12-09 15:46:24 +01:00
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DT_INST_FOREACH_STATUS_OKAY(HAS_HFC_OR) 0
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2022-09-07 10:57:12 +02:00
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#if UART_GECKO_USART_HW_FLOW_CONTROL_ENABLED || \
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2019-12-09 15:46:24 +01:00
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UART_GECKO_UART_HW_FLOW_CONTROL_ENABLED
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#define UART_GECKO_HW_FLOW_CONTROL
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#endif
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/* Sanity check for hardware flow control */
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2022-09-07 10:57:12 +02:00
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#if defined(UART_GECKO_HW_FLOW_CONTROL) && \
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2019-12-09 15:46:24 +01:00
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(!(defined(HW_FLOWCONTROL_IS_SUPPORTED_BY_SOC)))
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2022-09-07 10:57:12 +02:00
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#error "Hardware flow control is activated for at least one UART/USART, \
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2019-12-09 15:46:24 +01:00
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but not supported by this SOC"
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#endif
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2022-09-07 10:57:12 +02:00
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#if defined(UART_GECKO_HW_FLOW_CONTROL) && \
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(!defined(CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION) && \
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2021-09-24 13:26:22 +02:00
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!defined(GPIO_USART_ROUTEEN_RTSPEN))
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2019-12-09 15:46:24 +01:00
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#error "Driver not supporting hardware flow control for this SOC"
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#endif
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/**
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* @brief Config struct for UART
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*/
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2022-09-07 10:57:12 +02:00
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2017-04-05 19:06:17 +02:00
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struct uart_gecko_config {
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2022-09-07 10:57:12 +02:00
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#ifdef CONFIG_PINCTRL
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const struct pinctrl_dev_config *pcfg;
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#endif /* CONFIG_PINCTRL */
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2017-04-05 19:06:17 +02:00
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USART_TypeDef *base;
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CMU_Clock_TypeDef clock;
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2020-05-27 18:26:57 +02:00
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uint32_t baud_rate;
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2022-09-07 10:57:12 +02:00
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#ifndef CONFIG_PINCTRL
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2019-12-09 15:46:24 +01:00
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#ifdef UART_GECKO_HW_FLOW_CONTROL
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bool hw_flowcontrol;
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2022-09-07 10:57:12 +02:00
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#endif /* UART_GECKO_HW_FLOW_CONTROL */
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2019-12-09 15:46:24 +01:00
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#endif
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2017-04-05 19:06:17 +02:00
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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2020-07-14 17:02:00 +02:00
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void (*irq_config_func)(const struct device *dev);
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2022-09-07 10:57:12 +02:00
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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#ifndef CONFIG_PINCTRL
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2019-01-14 16:39:40 +01:00
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struct soc_gpio_pin pin_rx;
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struct soc_gpio_pin pin_tx;
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2019-12-09 15:46:24 +01:00
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#ifdef UART_GECKO_HW_FLOW_CONTROL
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struct soc_gpio_pin pin_rts;
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struct soc_gpio_pin pin_cts;
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2022-09-07 10:57:12 +02:00
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#endif /* UART_GECKO_HW_FLOW_CONTROL */
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2019-01-14 16:39:40 +01:00
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#ifdef CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
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2020-05-27 18:26:57 +02:00
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uint8_t loc_rx;
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uint8_t loc_tx;
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2019-12-09 15:46:24 +01:00
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#ifdef UART_GECKO_HW_FLOW_CONTROL
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uint8_t loc_rts;
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uint8_t loc_cts;
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2022-09-07 10:57:12 +02:00
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#endif /* UART_GECKO_HW_FLOW_CONTROL */
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#else /* CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION */
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2020-05-27 18:26:57 +02:00
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uint8_t loc;
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2022-09-07 10:57:12 +02:00
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#endif /* CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION */
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2017-04-05 19:06:17 +02:00
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#endif
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};
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struct uart_gecko_data {
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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2018-07-16 20:12:26 +02:00
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uart_irq_callback_user_data_t callback;
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void *cb_data;
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2017-04-05 19:06:17 +02:00
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#endif
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};
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2020-07-14 17:02:00 +02:00
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static int uart_gecko_poll_in(const struct device *dev, unsigned char *c)
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2017-04-05 19:06:17 +02:00
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{
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2020-05-28 20:44:16 +02:00
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const struct uart_gecko_config *config = dev->config;
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2020-05-27 18:26:57 +02:00
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uint32_t flags = USART_StatusGet(config->base);
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2017-04-05 19:06:17 +02:00
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if (flags & USART_STATUS_RXDATAV) {
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*c = USART_Rx(config->base);
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return 0;
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}
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return -1;
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}
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2020-07-14 17:02:00 +02:00
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static void uart_gecko_poll_out(const struct device *dev, unsigned char c)
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2017-04-05 19:06:17 +02:00
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{
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2020-05-28 20:44:16 +02:00
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const struct uart_gecko_config *config = dev->config;
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2017-04-05 19:06:17 +02:00
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USART_Tx(config->base, c);
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}
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2020-07-14 17:02:00 +02:00
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static int uart_gecko_err_check(const struct device *dev)
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2017-04-05 19:06:17 +02:00
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{
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2020-05-28 20:44:16 +02:00
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const struct uart_gecko_config *config = dev->config;
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2020-05-27 18:26:57 +02:00
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uint32_t flags = USART_IntGet(config->base);
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2017-04-05 19:06:17 +02:00
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int err = 0;
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if (flags & USART_IF_RXOF) {
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err |= UART_ERROR_OVERRUN;
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}
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if (flags & USART_IF_PERR) {
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err |= UART_ERROR_PARITY;
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}
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if (flags & USART_IF_FERR) {
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err |= UART_ERROR_FRAMING;
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}
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USART_IntClear(config->base, USART_IF_RXOF |
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USART_IF_PERR |
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USART_IF_FERR);
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return err;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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2020-07-14 17:02:00 +02:00
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static int uart_gecko_fifo_fill(const struct device *dev, const uint8_t *tx_data,
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2017-04-05 19:06:17 +02:00
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int len)
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{
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2020-05-28 20:44:16 +02:00
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const struct uart_gecko_config *config = dev->config;
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2020-05-27 18:26:57 +02:00
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uint8_t num_tx = 0U;
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2017-04-05 19:06:17 +02:00
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while ((len - num_tx > 0) &&
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(config->base->STATUS & USART_STATUS_TXBL)) {
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2020-05-27 18:26:57 +02:00
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config->base->TXDATA = (uint32_t)tx_data[num_tx++];
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2017-04-05 19:06:17 +02:00
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}
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return num_tx;
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}
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2020-07-14 17:02:00 +02:00
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static int uart_gecko_fifo_read(const struct device *dev, uint8_t *rx_data,
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2017-04-05 19:06:17 +02:00
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const int len)
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{
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2020-05-28 20:44:16 +02:00
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const struct uart_gecko_config *config = dev->config;
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2020-05-27 18:26:57 +02:00
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uint8_t num_rx = 0U;
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2017-04-05 19:06:17 +02:00
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while ((len - num_rx > 0) &&
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(config->base->STATUS & USART_STATUS_RXDATAV)) {
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2020-05-27 18:26:57 +02:00
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rx_data[num_rx++] = (uint8_t)config->base->RXDATA;
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2017-04-05 19:06:17 +02:00
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}
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return num_rx;
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}
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2020-07-14 17:02:00 +02:00
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static void uart_gecko_irq_tx_enable(const struct device *dev)
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2017-04-05 19:06:17 +02:00
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{
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2020-05-28 20:44:16 +02:00
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const struct uart_gecko_config *config = dev->config;
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2020-05-27 18:26:57 +02:00
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uint32_t mask = USART_IEN_TXBL | USART_IEN_TXC;
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2017-04-05 19:06:17 +02:00
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USART_IntEnable(config->base, mask);
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}
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2020-07-14 17:02:00 +02:00
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static void uart_gecko_irq_tx_disable(const struct device *dev)
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2017-04-05 19:06:17 +02:00
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{
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2020-05-28 20:44:16 +02:00
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const struct uart_gecko_config *config = dev->config;
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2020-05-27 18:26:57 +02:00
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uint32_t mask = USART_IEN_TXBL | USART_IEN_TXC;
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2017-04-05 19:06:17 +02:00
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USART_IntDisable(config->base, mask);
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}
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2020-07-14 17:02:00 +02:00
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static int uart_gecko_irq_tx_complete(const struct device *dev)
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2017-04-05 19:06:17 +02:00
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{
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2020-05-28 20:44:16 +02:00
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const struct uart_gecko_config *config = dev->config;
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2020-05-27 18:26:57 +02:00
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uint32_t flags = USART_IntGet(config->base);
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2017-04-05 19:06:17 +02:00
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USART_IntClear(config->base, USART_IF_TXC);
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2019-03-27 02:57:45 +01:00
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return (flags & USART_IF_TXC) != 0U;
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2017-04-05 19:06:17 +02:00
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}
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2020-07-14 17:02:00 +02:00
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static int uart_gecko_irq_tx_ready(const struct device *dev)
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2017-04-05 19:06:17 +02:00
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{
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2020-05-28 20:44:16 +02:00
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const struct uart_gecko_config *config = dev->config;
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2020-07-14 17:36:57 +02:00
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uint32_t flags = USART_IntGetEnabled(config->base);
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2017-04-05 19:06:17 +02:00
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2019-03-27 02:57:45 +01:00
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return (flags & USART_IF_TXBL) != 0U;
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2017-04-05 19:06:17 +02:00
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}
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2020-07-14 17:02:00 +02:00
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static void uart_gecko_irq_rx_enable(const struct device *dev)
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2017-04-05 19:06:17 +02:00
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{
|
2020-05-28 20:44:16 +02:00
|
|
|
const struct uart_gecko_config *config = dev->config;
|
2020-05-27 18:26:57 +02:00
|
|
|
uint32_t mask = USART_IEN_RXDATAV;
|
2017-04-05 19:06:17 +02:00
|
|
|
|
|
|
|
USART_IntEnable(config->base, mask);
|
|
|
|
}
|
|
|
|
|
2020-07-14 17:02:00 +02:00
|
|
|
static void uart_gecko_irq_rx_disable(const struct device *dev)
|
2017-04-05 19:06:17 +02:00
|
|
|
{
|
2020-05-28 20:44:16 +02:00
|
|
|
const struct uart_gecko_config *config = dev->config;
|
2020-05-27 18:26:57 +02:00
|
|
|
uint32_t mask = USART_IEN_RXDATAV;
|
2017-04-05 19:06:17 +02:00
|
|
|
|
|
|
|
USART_IntDisable(config->base, mask);
|
|
|
|
}
|
|
|
|
|
2020-07-14 17:02:00 +02:00
|
|
|
static int uart_gecko_irq_rx_full(const struct device *dev)
|
2017-04-05 19:06:17 +02:00
|
|
|
{
|
2020-05-28 20:44:16 +02:00
|
|
|
const struct uart_gecko_config *config = dev->config;
|
2020-05-27 18:26:57 +02:00
|
|
|
uint32_t flags = USART_IntGet(config->base);
|
2017-04-05 19:06:17 +02:00
|
|
|
|
2019-03-27 02:57:45 +01:00
|
|
|
return (flags & USART_IF_RXDATAV) != 0U;
|
2017-04-05 19:06:17 +02:00
|
|
|
}
|
|
|
|
|
2020-07-14 17:02:00 +02:00
|
|
|
static int uart_gecko_irq_rx_ready(const struct device *dev)
|
2017-04-05 19:06:17 +02:00
|
|
|
{
|
2020-05-28 20:44:16 +02:00
|
|
|
const struct uart_gecko_config *config = dev->config;
|
2020-05-27 18:26:57 +02:00
|
|
|
uint32_t mask = USART_IEN_RXDATAV;
|
2017-04-05 19:06:17 +02:00
|
|
|
|
|
|
|
return (config->base->IEN & mask)
|
|
|
|
&& uart_gecko_irq_rx_full(dev);
|
|
|
|
}
|
|
|
|
|
2020-07-14 17:02:00 +02:00
|
|
|
static void uart_gecko_irq_err_enable(const struct device *dev)
|
2017-04-05 19:06:17 +02:00
|
|
|
{
|
2020-05-28 20:44:16 +02:00
|
|
|
const struct uart_gecko_config *config = dev->config;
|
2017-04-05 19:06:17 +02:00
|
|
|
|
|
|
|
USART_IntEnable(config->base, USART_IF_RXOF |
|
|
|
|
USART_IF_PERR |
|
|
|
|
USART_IF_FERR);
|
|
|
|
}
|
|
|
|
|
2020-07-14 17:02:00 +02:00
|
|
|
static void uart_gecko_irq_err_disable(const struct device *dev)
|
2017-04-05 19:06:17 +02:00
|
|
|
{
|
2020-05-28 20:44:16 +02:00
|
|
|
const struct uart_gecko_config *config = dev->config;
|
2017-04-05 19:06:17 +02:00
|
|
|
|
|
|
|
USART_IntDisable(config->base, USART_IF_RXOF |
|
|
|
|
USART_IF_PERR |
|
|
|
|
USART_IF_FERR);
|
|
|
|
}
|
|
|
|
|
2020-07-14 17:02:00 +02:00
|
|
|
static int uart_gecko_irq_is_pending(const struct device *dev)
|
2017-04-05 19:06:17 +02:00
|
|
|
{
|
|
|
|
return uart_gecko_irq_tx_ready(dev) || uart_gecko_irq_rx_ready(dev);
|
|
|
|
}
|
|
|
|
|
2020-07-14 17:02:00 +02:00
|
|
|
static int uart_gecko_irq_update(const struct device *dev)
|
2017-04-05 19:06:17 +02:00
|
|
|
{
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2020-07-14 17:02:00 +02:00
|
|
|
static void uart_gecko_irq_callback_set(const struct device *dev,
|
2018-07-16 20:12:26 +02:00
|
|
|
uart_irq_callback_user_data_t cb,
|
|
|
|
void *cb_data)
|
2017-04-05 19:06:17 +02:00
|
|
|
{
|
2020-05-28 21:23:02 +02:00
|
|
|
struct uart_gecko_data *data = dev->data;
|
2017-04-05 19:06:17 +02:00
|
|
|
|
|
|
|
data->callback = cb;
|
2018-07-16 20:12:26 +02:00
|
|
|
data->cb_data = cb_data;
|
2017-04-05 19:06:17 +02:00
|
|
|
}
|
|
|
|
|
isr: Normalize usage of device instance through ISR
The goal of this patch is to replace the 'void *' parameter by 'struct
device *' if they use such variable or just 'const void *' on all
relevant ISRs
This will avoid not-so-nice const qualifier tweaks when device instances
will be constant.
Note that only the ISR passed to IRQ_CONNECT are of interest here.
In order to do so, the script fix_isr.py below is necessary:
from pathlib import Path
import subprocess
import pickle
import mmap
import sys
import re
import os
cocci_template = """
@r_fix_isr_0
@
type ret_type;
identifier P;
identifier D;
@@
-ret_type <!fn!>(void *P)
+ret_type <!fn!>(const struct device *P)
{
...
(
const struct device *D = (const struct device *)P;
|
const struct device *D = P;
)
...
}
@r_fix_isr_1
@
type ret_type;
identifier P;
identifier D;
@@
-ret_type <!fn!>(void *P)
+ret_type <!fn!>(const struct device *P)
{
...
const struct device *D;
...
(
D = (const struct device *)P;
|
D = P;
)
...
}
@r_fix_isr_2
@
type ret_type;
identifier A;
@@
-ret_type <!fn!>(void *A)
+ret_type <!fn!>(const void *A)
{
...
}
@r_fix_isr_3
@
const struct device *D;
@@
-<!fn!>((void *)D);
+<!fn!>(D);
@r_fix_isr_4
@
type ret_type;
identifier D;
identifier P;
@@
-ret_type <!fn!>(const struct device *P)
+ret_type <!fn!>(const struct device *D)
{
...
(
-const struct device *D = (const struct device *)P;
|
-const struct device *D = P;
)
...
}
@r_fix_isr_5
@
type ret_type;
identifier D;
identifier P;
@@
-ret_type <!fn!>(const struct device *P)
+ret_type <!fn!>(const struct device *D)
{
...
-const struct device *D;
...
(
-D = (const struct device *)P;
|
-D = P;
)
...
}
"""
def find_isr(fn):
db = []
data = None
start = 0
try:
with open(fn, 'r+') as f:
data = str(mmap.mmap(f.fileno(), 0).read())
except Exception as e:
return db
while True:
isr = ""
irq = data.find('IRQ_CONNECT', start)
while irq > -1:
p = 1
arg = 1
p_o = data.find('(', irq)
if p_o < 0:
irq = -1
break;
pos = p_o + 1
while p > 0:
if data[pos] == ')':
p -= 1
elif data[pos] == '(':
p += 1
elif data[pos] == ',' and p == 1:
arg += 1
if arg == 3:
isr += data[pos]
pos += 1
isr = isr.strip(',\\n\\t ')
if isr not in db and len(isr) > 0:
db.append(isr)
start = pos
break
if irq < 0:
break
return db
def patch_isr(fn, isr_list):
if len(isr_list) <= 0:
return
for isr in isr_list:
tmplt = cocci_template.replace('<!fn!>', isr)
with open('/tmp/isr_fix.cocci', 'w') as f:
f.write(tmplt)
cmd = ['spatch', '--sp-file', '/tmp/isr_fix.cocci', '--in-place', fn]
subprocess.run(cmd)
def process_files(path):
if path.is_file() and path.suffix in ['.h', '.c']:
p = str(path.parent) + '/' + path.name
isr_list = find_isr(p)
patch_isr(p, isr_list)
elif path.is_dir():
for p in path.iterdir():
process_files(p)
if len(sys.argv) < 2:
print("You need to provide a dir/file path")
sys.exit(1)
process_files(Path(sys.argv[1]))
And is run: ./fix_isr.py <zephyr root directory>
Finally, some files needed manual fixes such.
Fixes #27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-06-17 14:58:56 +02:00
|
|
|
static void uart_gecko_isr(const struct device *dev)
|
2017-04-05 19:06:17 +02:00
|
|
|
{
|
2020-05-28 21:23:02 +02:00
|
|
|
struct uart_gecko_data *data = dev->data;
|
2017-04-05 19:06:17 +02:00
|
|
|
|
|
|
|
if (data->callback) {
|
2020-06-24 15:47:15 +02:00
|
|
|
data->callback(dev, data->cb_data);
|
2017-04-05 19:06:17 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
|
|
|
|
|
2019-12-09 15:46:24 +01:00
|
|
|
/**
|
|
|
|
* @brief Subroutine initializer of UART pins
|
|
|
|
*
|
|
|
|
* @param dev UART device to configure
|
|
|
|
*/
|
2022-09-07 10:57:12 +02:00
|
|
|
#ifndef CONFIG_PINCTRL
|
2020-07-14 17:02:00 +02:00
|
|
|
static void uart_gecko_init_pins(const struct device *dev)
|
2017-04-05 19:06:17 +02:00
|
|
|
{
|
2020-05-28 20:44:16 +02:00
|
|
|
const struct uart_gecko_config *config = dev->config;
|
2017-04-05 19:06:17 +02:00
|
|
|
|
2019-12-09 15:46:24 +01:00
|
|
|
/* Configure RX and TX */
|
2022-10-24 10:20:45 +02:00
|
|
|
GPIO_PinModeSet(config->pin_rx.port, config->pin_rx.pin,
|
|
|
|
config->pin_rx.mode, config->pin_rx.out);
|
|
|
|
GPIO_PinModeSet(config->pin_tx.port, config->pin_tx.pin,
|
|
|
|
config->pin_tx.mode, config->pin_tx.out);
|
2019-12-09 15:46:24 +01:00
|
|
|
|
2019-01-14 16:39:40 +01:00
|
|
|
#ifdef CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
|
2019-12-09 15:46:24 +01:00
|
|
|
/* For SOCs with configurable pin locations (set in SOC Kconfig) */
|
2018-03-27 12:25:19 +02:00
|
|
|
config->base->ROUTEPEN = USART_ROUTEPEN_RXPEN | USART_ROUTEPEN_TXPEN;
|
2018-10-16 18:51:01 +02:00
|
|
|
config->base->ROUTELOC0 =
|
2019-01-14 16:39:40 +01:00
|
|
|
(config->loc_tx << _USART_ROUTELOC0_TXLOC_SHIFT) |
|
|
|
|
(config->loc_rx << _USART_ROUTELOC0_RXLOC_SHIFT);
|
2018-03-27 12:25:19 +02:00
|
|
|
config->base->ROUTELOC1 = _USART_ROUTELOC1_RESETVALUE;
|
2020-07-14 11:39:42 +02:00
|
|
|
#elif defined(USART_ROUTE_RXPEN) && defined(USART_ROUTE_TXPEN)
|
2019-12-09 15:46:24 +01:00
|
|
|
/* For olders SOCs with only one pin location */
|
2017-04-05 19:06:17 +02:00
|
|
|
config->base->ROUTE = USART_ROUTE_RXPEN | USART_ROUTE_TXPEN
|
|
|
|
| (config->loc << 8);
|
2020-07-14 11:39:42 +02:00
|
|
|
#elif defined(GPIO_USART_ROUTEEN_RXPEN) && defined(GPIO_USART_ROUTEEN_TXPEN)
|
|
|
|
GPIO->USARTROUTE[USART_NUM(config->base)].ROUTEEN =
|
|
|
|
GPIO_USART_ROUTEEN_TXPEN | GPIO_USART_ROUTEEN_RXPEN;
|
|
|
|
GPIO->USARTROUTE[USART_NUM(config->base)].TXROUTE =
|
|
|
|
(config->pin_tx.pin << _GPIO_USART_TXROUTE_PIN_SHIFT) |
|
|
|
|
(config->pin_tx.port << _GPIO_USART_TXROUTE_PORT_SHIFT);
|
|
|
|
GPIO->USARTROUTE[USART_NUM(config->base)].RXROUTE =
|
|
|
|
(config->pin_rx.pin << _GPIO_USART_RXROUTE_PIN_SHIFT) |
|
|
|
|
(config->pin_rx.port << _GPIO_USART_RXROUTE_PORT_SHIFT);
|
2019-12-09 15:46:24 +01:00
|
|
|
#endif /* CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION */
|
|
|
|
|
|
|
|
#ifdef UART_GECKO_HW_FLOW_CONTROL
|
|
|
|
/* Configure HW flow control (RTS, CTS) */
|
|
|
|
if (config->hw_flowcontrol) {
|
2022-10-24 10:20:45 +02:00
|
|
|
GPIO_PinModeSet(config->pin_rts.port, config->pin_rts.pin,
|
|
|
|
config->pin_rts.mode, config->pin_rts.out);
|
|
|
|
GPIO_PinModeSet(config->pin_cts.port, config->pin_cts.pin,
|
|
|
|
config->pin_cts.mode, config->pin_cts.out);
|
2019-12-09 15:46:24 +01:00
|
|
|
|
|
|
|
#ifdef CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
|
|
|
|
config->base->ROUTEPEN =
|
|
|
|
USART_ROUTEPEN_RXPEN |
|
|
|
|
USART_ROUTEPEN_TXPEN |
|
|
|
|
USART_ROUTEPEN_RTSPEN |
|
|
|
|
USART_ROUTEPEN_CTSPEN;
|
|
|
|
|
|
|
|
config->base->ROUTELOC1 =
|
|
|
|
(config->loc_rts << _USART_ROUTELOC1_RTSLOC_SHIFT) |
|
|
|
|
(config->loc_cts << _USART_ROUTELOC1_CTSLOC_SHIFT);
|
|
|
|
#elif defined(GPIO_USART_ROUTEEN_RTSPEN) && defined(GPIO_USART_ROUTEEN_CTSPEN)
|
|
|
|
GPIO->USARTROUTE[USART_NUM(config->base)].ROUTEEN =
|
|
|
|
GPIO_USART_ROUTEEN_TXPEN |
|
|
|
|
GPIO_USART_ROUTEEN_RXPEN |
|
|
|
|
GPIO_USART_ROUTEPEN_RTSPEN |
|
|
|
|
GPIO_USART_ROUTEPEN_CTSPEN;
|
|
|
|
|
|
|
|
GPIO->USARTROUTE[USART_NUM(config->base)].RTSROUTE =
|
|
|
|
(config->pin_rts.pin << _GPIO_USART_RTSROUTE_PIN_SHIFT) |
|
|
|
|
(config->pin_rts.port << _GPIO_USART_RTSROUTE_PORT_SHIFT);
|
|
|
|
GPIO->USARTROUTE[USART_NUM(config->base)].CTSROUTE =
|
|
|
|
(config->pin_cts.pin << _GPIO_USART_CTSROUTE_PIN_SHIFT) |
|
|
|
|
(config->pin_cts.port << _GPIO_USART_CTSROUTE_PORT_SHIFT);
|
|
|
|
#endif /* CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION */
|
|
|
|
}
|
|
|
|
#endif /* UART_GECKO_HW_FLOW_CONTROL */
|
2017-04-05 19:06:17 +02:00
|
|
|
}
|
2022-09-07 10:57:12 +02:00
|
|
|
#endif /* !CONFIG_PINCTRL */
|
2017-04-05 19:06:17 +02:00
|
|
|
|
2019-12-09 15:46:24 +01:00
|
|
|
/**
|
|
|
|
* @brief Main initializer for UART
|
|
|
|
*
|
|
|
|
* @param dev UART device to be initialized
|
|
|
|
* @return int 0
|
|
|
|
*/
|
2020-07-14 17:02:00 +02:00
|
|
|
static int uart_gecko_init(const struct device *dev)
|
2017-04-05 19:06:17 +02:00
|
|
|
{
|
2022-09-07 10:57:12 +02:00
|
|
|
#ifdef CONFIG_PINCTRL
|
|
|
|
int err;
|
|
|
|
#endif /* CONFIG_PINCTRL */
|
2020-05-28 20:44:16 +02:00
|
|
|
const struct uart_gecko_config *config = dev->config;
|
2022-09-07 10:57:12 +02:00
|
|
|
|
2017-04-05 19:06:17 +02:00
|
|
|
USART_InitAsync_TypeDef usartInit = USART_INITASYNC_DEFAULT;
|
|
|
|
|
|
|
|
/* The peripheral and gpio clock are already enabled from soc and gpio
|
|
|
|
* driver
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* Enable USART clock */
|
|
|
|
CMU_ClockEnable(config->clock, true);
|
|
|
|
|
|
|
|
/* Init USART */
|
2019-12-09 15:46:24 +01:00
|
|
|
usartInit.baudrate = config->baud_rate;
|
|
|
|
#ifdef UART_GECKO_HW_FLOW_CONTROL
|
|
|
|
usartInit.hwFlowControl = config->hw_flowcontrol ?
|
|
|
|
usartHwFlowControlCtsAndRts : usartHwFlowControlNone;
|
|
|
|
#endif
|
2017-04-05 19:06:17 +02:00
|
|
|
USART_InitAsync(config->base, &usartInit);
|
|
|
|
|
2022-09-07 10:57:12 +02:00
|
|
|
#ifdef CONFIG_PINCTRL
|
|
|
|
err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
|
|
|
|
if (err < 0) {
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
#else
|
2017-04-05 19:06:17 +02:00
|
|
|
/* Initialize USART pins */
|
|
|
|
uart_gecko_init_pins(dev);
|
2022-09-07 10:57:12 +02:00
|
|
|
#endif /* CONFIG_PINCTRL */
|
2017-04-05 19:06:17 +02:00
|
|
|
|
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
|
|
config->irq_config_func(dev);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct uart_driver_api uart_gecko_driver_api = {
|
|
|
|
.poll_in = uart_gecko_poll_in,
|
|
|
|
.poll_out = uart_gecko_poll_out,
|
|
|
|
.err_check = uart_gecko_err_check,
|
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
|
|
.fifo_fill = uart_gecko_fifo_fill,
|
|
|
|
.fifo_read = uart_gecko_fifo_read,
|
|
|
|
.irq_tx_enable = uart_gecko_irq_tx_enable,
|
|
|
|
.irq_tx_disable = uart_gecko_irq_tx_disable,
|
|
|
|
.irq_tx_complete = uart_gecko_irq_tx_complete,
|
|
|
|
.irq_tx_ready = uart_gecko_irq_tx_ready,
|
|
|
|
.irq_rx_enable = uart_gecko_irq_rx_enable,
|
|
|
|
.irq_rx_disable = uart_gecko_irq_rx_disable,
|
|
|
|
.irq_rx_ready = uart_gecko_irq_rx_ready,
|
|
|
|
.irq_err_enable = uart_gecko_irq_err_enable,
|
|
|
|
.irq_err_disable = uart_gecko_irq_err_disable,
|
|
|
|
.irq_is_pending = uart_gecko_irq_is_pending,
|
|
|
|
.irq_update = uart_gecko_irq_update,
|
|
|
|
.irq_callback_set = uart_gecko_irq_callback_set,
|
|
|
|
#endif
|
|
|
|
};
|
|
|
|
|
2019-12-09 15:46:24 +01:00
|
|
|
#undef DT_DRV_COMPAT
|
2020-03-24 20:49:56 +01:00
|
|
|
#define DT_DRV_COMPAT silabs_gecko_uart
|
2019-01-14 16:39:40 +01:00
|
|
|
|
2017-04-05 19:06:17 +02:00
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
2020-06-04 16:37:51 +02:00
|
|
|
#define GECKO_UART_IRQ_HANDLER_DECL(idx) \
|
2020-07-14 17:02:00 +02:00
|
|
|
static void uart_gecko_config_func_##idx(const struct device *dev)
|
2020-06-04 16:37:51 +02:00
|
|
|
#define GECKO_UART_IRQ_HANDLER_FUNC(idx) \
|
|
|
|
.irq_config_func = uart_gecko_config_func_##idx,
|
|
|
|
#define GECKO_UART_IRQ_HANDLER(idx) \
|
2022-09-07 10:57:12 +02:00
|
|
|
static void uart_gecko_config_func_##idx(const struct device *dev) \
|
2020-06-04 16:37:51 +02:00
|
|
|
{ \
|
|
|
|
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(idx, rx, irq), \
|
|
|
|
DT_INST_IRQ_BY_NAME(idx, rx, priority), \
|
2020-12-11 17:12:30 +01:00
|
|
|
uart_gecko_isr, DEVICE_DT_INST_GET(idx), 0); \
|
2020-06-04 16:37:51 +02:00
|
|
|
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(idx, tx, irq), \
|
|
|
|
DT_INST_IRQ_BY_NAME(idx, tx, priority), \
|
2020-12-11 17:12:30 +01:00
|
|
|
uart_gecko_isr, DEVICE_DT_INST_GET(idx), 0); \
|
2020-06-04 16:37:51 +02:00
|
|
|
\
|
|
|
|
irq_enable(DT_INST_IRQ_BY_NAME(idx, rx, irq)); \
|
|
|
|
irq_enable(DT_INST_IRQ_BY_NAME(idx, tx, irq)); \
|
|
|
|
}
|
2019-12-09 15:46:24 +01:00
|
|
|
#else /* CONFIG_UART_INTERRUPT_DRIVEN */
|
2020-06-04 16:37:51 +02:00
|
|
|
#define GECKO_UART_IRQ_HANDLER_DECL(idx)
|
|
|
|
#define GECKO_UART_IRQ_HANDLER_FUNC(idx)
|
|
|
|
#define GECKO_UART_IRQ_HANDLER(idx)
|
2019-12-09 15:46:24 +01:00
|
|
|
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
|
2017-04-05 19:06:17 +02:00
|
|
|
|
2019-01-14 16:39:40 +01:00
|
|
|
#ifdef CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
|
2019-12-09 15:46:24 +01:00
|
|
|
#define GECKO_UART_RX_TX_PIN_LOCATIONS(idx) \
|
2020-06-04 16:37:51 +02:00
|
|
|
.loc_rx = DT_INST_PROP_BY_IDX(idx, location_rx, 0), \
|
|
|
|
.loc_tx = DT_INST_PROP_BY_IDX(idx, location_tx, 0),
|
2019-12-09 15:46:24 +01:00
|
|
|
#define VALIDATE_GECKO_UART_RX_TX_PIN_LOCATIONS(idx)
|
2019-01-14 16:39:40 +01:00
|
|
|
#else
|
2019-12-09 15:46:24 +01:00
|
|
|
#define GECKO_UART_RX_TX_PIN_LOCATIONS(idx) \
|
2020-06-04 16:37:51 +02:00
|
|
|
.loc = DT_INST_PROP_BY_IDX(idx, location_rx, 0),
|
2019-12-09 15:46:24 +01:00
|
|
|
#define VALIDATE_GECKO_UART_RX_TX_PIN_LOCATIONS(idx) \
|
2020-06-04 16:37:51 +02:00
|
|
|
BUILD_ASSERT(DT_INST_PROP_BY_IDX(idx, location_rx, 0) == \
|
|
|
|
DT_INST_PROP_BY_IDX(idx, location_tx, 0), \
|
|
|
|
"DTS location-* properties must have identical value")
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#define PIN_UART_RXD(idx) \
|
|
|
|
{ \
|
|
|
|
DT_INST_PROP_BY_IDX(idx, location_rx, 1), \
|
|
|
|
DT_INST_PROP_BY_IDX(idx, location_rx, 2), \
|
|
|
|
gpioModeInput, 1 \
|
|
|
|
}
|
|
|
|
#define PIN_UART_TXD(idx) \
|
|
|
|
{ \
|
|
|
|
DT_INST_PROP_BY_IDX(idx, location_tx, 1), \
|
|
|
|
DT_INST_PROP_BY_IDX(idx, location_tx, 2), \
|
|
|
|
gpioModePushPull, 1 \
|
|
|
|
}
|
2017-04-05 19:06:17 +02:00
|
|
|
|
2019-12-09 15:46:24 +01:00
|
|
|
#define GECKO_UART_RX_TX_PINS(idx) \
|
2020-06-04 16:37:51 +02:00
|
|
|
.pin_rx = PIN_UART_RXD(idx), \
|
|
|
|
.pin_tx = PIN_UART_TXD(idx),
|
|
|
|
|
2019-12-09 15:46:24 +01:00
|
|
|
#ifdef UART_GECKO_HW_FLOW_CONTROL
|
|
|
|
|
|
|
|
#ifdef CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
|
|
|
|
#define GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx) \
|
|
|
|
.loc_rts = COND_CODE_1(DT_INST_PROP(idx, hw_flow_control), \
|
|
|
|
(DT_INST_PROP_BY_IDX(idx, location_rts, 0)), \
|
|
|
|
(0)), \
|
|
|
|
.loc_cts = COND_CODE_1(DT_INST_PROP(idx, hw_flow_control), \
|
|
|
|
(DT_INST_PROP_BY_IDX(idx, location_cts, 0)), \
|
|
|
|
(0)),
|
|
|
|
#define VALIDATE_GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx) \
|
|
|
|
COND_CODE_1(DT_INST_PROP(idx, hw_flow_control), \
|
|
|
|
(BUILD_ASSERT(DT_INST_NODE_HAS_PROP(idx, location_rts) && \
|
|
|
|
DT_INST_NODE_HAS_PROP(idx, location_cts), \
|
|
|
|
"DTS location-rts and location-cts are mandatory")), \
|
|
|
|
())
|
|
|
|
#else /* CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION */
|
|
|
|
/* Hardware flow control not supported for these SOCs */
|
|
|
|
#define GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx)
|
|
|
|
#define VALIDATE_GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx)
|
|
|
|
#endif /* CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION */
|
|
|
|
|
|
|
|
#define PIN_UART_RTS(idx) \
|
|
|
|
COND_CODE_1(DT_INST_PROP(idx, hw_flow_control), \
|
|
|
|
({ \
|
|
|
|
DT_INST_PROP_BY_IDX(idx, location_rts, 1), \
|
|
|
|
DT_INST_PROP_BY_IDX(idx, location_rts, 2), \
|
|
|
|
gpioModePushPull, 1 \
|
|
|
|
}), \
|
|
|
|
({0}))
|
|
|
|
|
|
|
|
#define PIN_UART_CTS(idx) \
|
|
|
|
COND_CODE_1(DT_INST_PROP(idx, hw_flow_control), \
|
|
|
|
({ \
|
|
|
|
DT_INST_PROP_BY_IDX(idx, location_cts, 1), \
|
|
|
|
DT_INST_PROP_BY_IDX(idx, location_cts, 2), \
|
|
|
|
gpioModeInput, 1 \
|
|
|
|
}), \
|
|
|
|
({0}))
|
|
|
|
|
|
|
|
#define GECKO_UART_RTS_CTS_PINS(idx) \
|
|
|
|
.pin_rts = PIN_UART_RTS(idx), \
|
|
|
|
.pin_cts = PIN_UART_CTS(idx),
|
|
|
|
|
|
|
|
#define GECKO_UART_HW_FLOW_CONTROL(idx) \
|
|
|
|
.hw_flowcontrol = DT_INST_PROP(idx, hw_flow_control),
|
|
|
|
|
|
|
|
#else /* UART_GECKO_HW_FLOW_CONTROL */
|
|
|
|
|
|
|
|
#define GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx)
|
|
|
|
#define VALIDATE_GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx)
|
|
|
|
#define GECKO_UART_RTS_CTS_PINS(idx)
|
|
|
|
#define GECKO_UART_HW_FLOW_CONTROL(idx)
|
|
|
|
|
|
|
|
#endif /* UART_GECKO_HW_FLOW_CONTROL */
|
|
|
|
|
2020-06-04 16:37:51 +02:00
|
|
|
#define GECKO_UART_INIT(idx) \
|
2019-12-09 15:46:24 +01:00
|
|
|
VALIDATE_GECKO_UART_RX_TX_PIN_LOCATIONS(idx); \
|
|
|
|
VALIDATE_GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx); \
|
|
|
|
\
|
2020-06-04 16:37:51 +02:00
|
|
|
GECKO_UART_IRQ_HANDLER_DECL(idx); \
|
|
|
|
\
|
|
|
|
static const struct uart_gecko_config uart_gecko_cfg_##idx = { \
|
|
|
|
.base = (USART_TypeDef *)DT_INST_REG_ADDR(idx), \
|
2022-10-31 09:43:19 +01:00
|
|
|
.clock = GET_GECKO_UART_CLOCK(idx), \
|
2020-06-04 16:37:51 +02:00
|
|
|
.baud_rate = DT_INST_PROP(idx, current_speed), \
|
2019-12-09 15:46:24 +01:00
|
|
|
GECKO_UART_HW_FLOW_CONTROL(idx) \
|
|
|
|
GECKO_UART_RX_TX_PINS(idx) \
|
|
|
|
GECKO_UART_RTS_CTS_PINS(idx) \
|
|
|
|
GECKO_UART_RX_TX_PIN_LOCATIONS(idx) \
|
|
|
|
GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx) \
|
2020-06-04 16:37:51 +02:00
|
|
|
GECKO_UART_IRQ_HANDLER_FUNC(idx) \
|
|
|
|
}; \
|
|
|
|
\
|
|
|
|
static struct uart_gecko_data uart_gecko_data_##idx; \
|
|
|
|
\
|
2020-12-11 17:12:30 +01:00
|
|
|
DEVICE_DT_INST_DEFINE(idx, &uart_gecko_init, \
|
2021-04-28 12:01:21 +02:00
|
|
|
NULL, &uart_gecko_data_##idx, \
|
2020-06-04 16:37:51 +02:00
|
|
|
&uart_gecko_cfg_##idx, PRE_KERNEL_1, \
|
2021-10-14 16:38:10 +02:00
|
|
|
CONFIG_SERIAL_INIT_PRIORITY, \
|
2020-06-04 16:37:51 +02:00
|
|
|
&uart_gecko_driver_api); \
|
|
|
|
\
|
|
|
|
\
|
|
|
|
GECKO_UART_IRQ_HANDLER(idx)
|
|
|
|
|
|
|
|
DT_INST_FOREACH_STATUS_OKAY(GECKO_UART_INIT)
|
2020-03-24 20:49:56 +01:00
|
|
|
|
|
|
|
#undef DT_DRV_COMPAT
|
|
|
|
#define DT_DRV_COMPAT silabs_gecko_usart
|
2019-01-14 16:39:40 +01:00
|
|
|
|
2018-10-16 18:51:01 +02:00
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
2020-06-04 16:37:51 +02:00
|
|
|
#define GECKO_USART_IRQ_HANDLER_DECL(idx) \
|
2020-07-14 17:02:00 +02:00
|
|
|
static void usart_gecko_config_func_##idx(const struct device *dev)
|
2020-06-04 16:37:51 +02:00
|
|
|
#define GECKO_USART_IRQ_HANDLER_FUNC(idx) \
|
|
|
|
.irq_config_func = usart_gecko_config_func_##idx,
|
|
|
|
#define GECKO_USART_IRQ_HANDLER(idx) \
|
2022-09-07 10:57:12 +02:00
|
|
|
static void usart_gecko_config_func_##idx(const struct device *dev) \
|
2020-06-04 16:37:51 +02:00
|
|
|
{ \
|
|
|
|
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(idx, rx, irq), \
|
|
|
|
DT_INST_IRQ_BY_NAME(idx, rx, priority), \
|
2020-12-11 17:12:30 +01:00
|
|
|
uart_gecko_isr, DEVICE_DT_INST_GET(idx), 0); \
|
2020-06-04 16:37:51 +02:00
|
|
|
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(idx, tx, irq), \
|
|
|
|
DT_INST_IRQ_BY_NAME(idx, tx, priority), \
|
2020-12-11 17:12:30 +01:00
|
|
|
uart_gecko_isr, DEVICE_DT_INST_GET(idx), 0); \
|
2020-06-04 16:37:51 +02:00
|
|
|
\
|
|
|
|
irq_enable(DT_INST_IRQ_BY_NAME(idx, rx, irq)); \
|
|
|
|
irq_enable(DT_INST_IRQ_BY_NAME(idx, tx, irq)); \
|
|
|
|
}
|
2019-11-29 21:37:44 +01:00
|
|
|
#else
|
2020-06-04 16:37:51 +02:00
|
|
|
#define GECKO_USART_IRQ_HANDLER_DECL(idx)
|
|
|
|
#define GECKO_USART_IRQ_HANDLER_FUNC(idx)
|
|
|
|
#define GECKO_USART_IRQ_HANDLER(idx)
|
|
|
|
#endif
|
|
|
|
|
2022-09-07 10:57:12 +02:00
|
|
|
#ifdef CONFIG_PINCTRL
|
|
|
|
#define GECKO_USART_INIT(idx) \
|
|
|
|
PINCTRL_DT_INST_DEFINE(idx); \
|
|
|
|
GECKO_USART_IRQ_HANDLER_DECL(idx); \
|
|
|
|
\
|
|
|
|
static const struct uart_gecko_config usart_gecko_cfg_##idx = { \
|
|
|
|
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
|
|
|
|
.base = (USART_TypeDef *)DT_INST_REG_ADDR(idx), \
|
2022-10-31 09:43:19 +01:00
|
|
|
.clock = GET_GECKO_USART_CLOCK(idx), \
|
2022-09-07 10:57:12 +02:00
|
|
|
.baud_rate = DT_INST_PROP(idx, current_speed), \
|
|
|
|
GECKO_USART_IRQ_HANDLER_FUNC(idx) \
|
|
|
|
}; \
|
|
|
|
\
|
|
|
|
static struct uart_gecko_data usart_gecko_data_##idx; \
|
|
|
|
\
|
|
|
|
DEVICE_DT_INST_DEFINE(idx, &uart_gecko_init, NULL, \
|
|
|
|
&usart_gecko_data_##idx, \
|
|
|
|
&usart_gecko_cfg_##idx, PRE_KERNEL_1, \
|
|
|
|
CONFIG_SERIAL_INIT_PRIORITY, \
|
|
|
|
&uart_gecko_driver_api); \
|
|
|
|
\
|
|
|
|
GECKO_USART_IRQ_HANDLER(idx)
|
|
|
|
#else
|
2020-06-04 16:37:51 +02:00
|
|
|
#define GECKO_USART_INIT(idx) \
|
2019-12-09 15:46:24 +01:00
|
|
|
VALIDATE_GECKO_UART_RX_TX_PIN_LOCATIONS(idx); \
|
|
|
|
VALIDATE_GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx); \
|
|
|
|
\
|
2020-06-04 16:37:51 +02:00
|
|
|
GECKO_USART_IRQ_HANDLER_DECL(idx); \
|
|
|
|
\
|
2022-09-07 10:57:12 +02:00
|
|
|
static const struct uart_gecko_config usart_gecko_cfg_##idx = { \
|
2020-06-04 16:37:51 +02:00
|
|
|
.base = (USART_TypeDef *)DT_INST_REG_ADDR(idx), \
|
2022-10-31 09:43:19 +01:00
|
|
|
.clock = GET_GECKO_USART_CLOCK(idx), \
|
2020-06-04 16:37:51 +02:00
|
|
|
.baud_rate = DT_INST_PROP(idx, current_speed), \
|
2019-12-09 15:46:24 +01:00
|
|
|
GECKO_UART_HW_FLOW_CONTROL(idx) \
|
|
|
|
GECKO_UART_RX_TX_PINS(idx) \
|
|
|
|
GECKO_UART_RTS_CTS_PINS(idx) \
|
|
|
|
GECKO_UART_RX_TX_PIN_LOCATIONS(idx) \
|
|
|
|
GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx) \
|
2020-06-04 16:37:51 +02:00
|
|
|
GECKO_USART_IRQ_HANDLER_FUNC(idx) \
|
|
|
|
}; \
|
|
|
|
\
|
|
|
|
static struct uart_gecko_data usart_gecko_data_##idx; \
|
|
|
|
\
|
2021-04-28 12:01:21 +02:00
|
|
|
DEVICE_DT_INST_DEFINE(idx, &uart_gecko_init, NULL, \
|
2020-12-11 17:12:30 +01:00
|
|
|
&usart_gecko_data_##idx, \
|
2020-06-04 16:37:51 +02:00
|
|
|
&usart_gecko_cfg_##idx, PRE_KERNEL_1, \
|
2021-10-14 16:38:10 +02:00
|
|
|
CONFIG_SERIAL_INIT_PRIORITY, \
|
2020-06-04 16:37:51 +02:00
|
|
|
&uart_gecko_driver_api); \
|
|
|
|
\
|
|
|
|
GECKO_USART_IRQ_HANDLER(idx)
|
2022-09-07 10:57:12 +02:00
|
|
|
#endif
|
2020-06-04 16:37:51 +02:00
|
|
|
|
|
|
|
DT_INST_FOREACH_STATUS_OKAY(GECKO_USART_INIT)
|