add gpio_intel driver with acpi based resource enumeration support.
Also updated test cases overlay with new dts entires.
Signed-off-by: Najumon B.A <najumon.ba@intel.com>
The SparkFun Pro Micro header pins are numbered D1, D0, GND, ... from top
left whereas the SparkFun Pro Micro RP2040 and the Adafruit KB2040 boards
are using gpio 0, 1, GND, ... , so the pro_micro: connector gpio-map of
these boards should reflect that.
Graphical Datasheet for SparkFun Pro Micro RP2040:
https://cdn.sparkfun.com/assets/e/2/7/6/b/ProMicroRP2040_Graphical_Datasheet.pdf
Graphical Datasheet for SparkFun Pro Micro:
https://cdn.sparkfun.com/assets/f/d/8/0/d/ProMicro16MHzv2.pdf
Pinout of the Adafruit KB2040:
https://learn.adafruit.com/assets/106984
Please note that the KB2040 uses CircuitPython pin labels D0, D1 which does
not seemt correspond to the Arduino labels D0 and D1 used by the Pro Micro.
Signed-off-by: Daniel Irekvist <ulmanyar@gmail.com>
Rename ad5592 files in dts, driver and include to ad559x and add support
for I2C bus which is required for AD5593.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Add irqs to rzt2m gpio bindings in order to add interrupt support to rzt2m
gpio driver and adds common gpio node to store interrupt config (irqs are
shared between ports)
Signed-off-by: Jakub Michalski <jmichalski@internships.antmicro.com>
Split up the driver for the low side switch BD8LB600FS into a GPIO
and MFD part.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
AXP192 features an EXTEN pin that is on output only.
This commit appends control of EXTEN pin to gpio functionality
of AXP192.
Port-Mapping is as follows:
- [0..4]: GPIO0..4
- [5]: EXTEN
Signed-off-by: Martin Kiepfer <mrmarteng@teleschirm.org>
Add a set of bindings that will be used in the nRF54H20 SoC definition.
Extend the existing GPIOTE binding with properties needed for this SoC.
Also do a tiny clean-up in the bindings added recently for nRF54L15
(HFXO and LFXO).
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/ethernet, gpio, i2c and
interrupt-controller.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
At chip startup, jtag pins are configured by default to enable
debug.
This configuration adds consumption and when using PM profile,
we can save ~40uA by resetting this configuration and setting pins
to analog mode.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
In some hardware designs it might happen that the reset signal
for the TLE9104 is not used only for this purpose, but instead for
instance to reset other devices at the same time. For such a hardware
design it is then necessary to make the reset GPIO optional. The reset
will have to be triggered earlier on.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
This implements the daisy chain feature of the low side switch
BD8LB600FS. The daisy chaining is in hardware achieved via
connecting the MISO and MOSI lines of multiple instances of the IC
in a row. It is implemented in the driver through a variable number
of GPIOs on one instance. Therefore, one device tree instance of the
IC will handle multiple daisy chained physical instances.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
When set, this GPIO controller has pins associated with the
keyboard controller. In this case the reg_gpcr property is
overloaded and used to write the keyboard GCTRL register
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add RGPIO gpio driver. This driver is used for i.MX93 and i.MX8ULP.
GPIO pinctrl, read/write and interrupt is supported. Runtime mmio
configuration is enabled, so no need for region definition in
mimx9/mmu_region.c
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
Add support for M5Stack AtomS3 Lite development board.
The AtomS3 Lite is a smaller version of the AtomS3 that
features only a StatusLED and no LCD display.
Signed-off-by: Martin Kiepfer <mrmarteng@teleschirm.org>
Added GPIOTE0, GPIOTE1 instances for legacy devices,
GPIOTE20, GPIOTE30 for Moonlight and GPIOTE130,
GPIOTE131 instances for Haltium.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Generic Connector for the apollo4p_evb
Ran tests/drivers/gpio/gpio_basic_api
Ambiq does not support DUAL Edged Interrupts.
Added Connector Usages as defined by the Ambiq BSP.
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
The gpio_pca953x gpio driver doesn't have
the input latch and interrupt mask
configuration which causes a lack of accessing
and using those features on an gpio expander
device. Fix it by adding input latch and
interrupt mask configurations in this driver.
Signed-off-by: Vudang Thaihai <vudang.thaihai@brillpower.com>
This Ambiq gpio binding provides the GPIO pin mapping for GPIO child
nodes tosolve the limitation of the maximum 32 pins handling in GPIO
driver API.
The gpio-bank nodes can be created under the gpio parent node.
Signed-off-by: Aaron Ye <aye@ambiq.com>
Add Renesas rzt2m gpio driver with basic functionality.
It supports pin mode configuration and writing/reading to/from gpio ports.
Includes dts changes to build blinky sample.
Signed-off-by: Jakub Michalski <jmichalski@internships.antmicro.com>
Add pinctrl to the Davinci GPIO driver to allow muxing pins dirctly
in this driver.
Also aligned the macro backslashes as line continuation character at
the end of each line with each at the same position and removed the
GPIO_DAVINCI_DEVICE_INIT macro which seems to be not used.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Add initial support for Renesas RA GPIO.
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
This commit adds basic support for m5stacks M-Bus extenions port that is
support my core and core2 module.
Signed-off-by: Martin Kiepfer <m.kiepfer@teleschirm.org>
The BCM2711 SoC exposes 58 GPIOs. The first 28 (bank 0) are accessible
to users via the 40-pin header, while the others (bank 1) are used for
controlling on-board peripherals.
This also update doc of `rpi_4b` board.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
Extend the NXP S32 GPIO driver to be able to route external interrupts
to either SIUL2 EIRQ interrupt controller or, when available on the
SoC, WKPU interrupt controller.
Since WKPU can support up to 64 external interrupt sources and SIUL2
EIRQ up to 32, gpio_get_pending_int() is removed and the interrupt
controller specific API must be used instead.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The Nuvoton NCT38xx is a multi-function device providing a TCPC
controller and a I/O expander (GPIO driver). Add a multi-function
driver to manage exclusive access to the device.
Tested with "twister -T tests/drivers/build_all/gpio".
Signed-off-by: Keith Short <keithshort@google.com>
Davinci gpio controller support to add various soc gpio
support (J721E, AM654).
TRM for J721e https://www.ti.com/lit/zip/spruil1
File: spruil1c.pdf
GPIO: section 12.1.2
BeagleBone AI_64 https://beagleboard.org/ai-64
Signed-off-by: Prashanth S <slpp95prashanth@yahoo.com>
AXP192 is a small power management IC, that also
features 5 GPIOS.
Besides GPIO driver this commit also includes needed modifications
in axp192 regulator and mfd driver as LDOIO0 functioanlity
is multiplexed with GPIO0 pin.
Signed-off-by: Martin Kiepfer <mrmarteng@teleschirm.org>
So far pin identifiers were named after CN7 and CN10 connector names on
Nucleo-64 boards. In case of Nucleo-144 there are ST Morpho connectors on
both sides, but bigger (up to 72 instead of 38 pins on each side). First 38
pins out of 72 on each side usually map to the same pins (e.g. PA5 being
13th pin on right ST Morpho connector). This means that single ST Morpho
connector definition will suffice.
Leaving CN7 and CN10 (name of pin headers on Nucleo-64 boards) is confusing
in context of Nucleo-144 boards, since corresponding pin headers are named
CN11 and CN12.
Rename:
* s/ST_MORPHO_CN7_/ST_MORPHO_L_/
* s/ST_MORPHO_CN10_/ST_MORPHO_R_/
so that pin identifiers make more sense in context of Nucleo-144 boards.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Adding support for the adafruit can picowbell shield for the
raspberry pi picoi. Also added nodelable for spi0 called 'pico_spi'
as well as an GPIO nexus node 'pico_header'
Signed-off-by: Joseph Yates <joeyatessecond@gmail.com>
All Nucleo boards provide the ST Morpho connector/header, which exposes
all pins of the MCU. It is tipically used in ST shields, so provide a
nexus node to allow creating generic shields.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
