During the migration to Hw model V2 the PR #63495
was not fully reported.
This change is adding the support Serial Wire / JTAG port pins
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fixes the following errors when sparse (SCA) is enabled:
soc/intel/intel_adsp/ace/power.c:46:12: warning:
cast removes address space '__cache' of expression
/soc/intel/intel_adsp/ace/power.c:48:9: warning:
incorrect type in argument 1 (different address spaces)
Fixes#70725
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Select the LPTIM clock source STM32_LPTIM_CLOCK to be
LSE or LSI depending on the DTS clocks property
of the stm32_lp_tick_source node.
This will also affect the SYS_CLOCK_TICKS_PER_SEC
depending on the lptim prescaler
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add SoC initialization to set the UART RDC permission in the early
phase, so that the it can be used by Zephyr on Cortex-A cores.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
To minimize time the CPU spends when preparing for sleep, make sure
the pending transactions are finished before calling `wfi`.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
The SOC name `imx8ulp` has been just a placeholder until
support for the SOC's ADSP (since this is the only core
that's supported in Zephyr) could be added to the NXP HAL.
Now that the support has been added, to make use of it, the
SOC name `imx8ulp` has to be changed to `mimx8ud7`. As such,
this commit does the following:
1) Introduces SOC part number configuration - needed
by some HAL headers.
2) Replaces all occurrences of `imx8ulp` (as the SOC
name) with `mimx8ud7`.
3) Enables `CONFIG_HAS_MCUX`.
4) Aligns all `CONFIG_SOC_` configurations with the
new SOC name.
5) Updates SOF hash. This is needed to fix build issues
caused by this name change. This is not done in a separate
commit to preserve bisectability.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Simple rename to align the kernel naming scheme. This is being
used throughout the tree, especially in the architecture code.
As this is not a private API internal to kernel, prefix it
appropriately with K_.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Doing a `GCLK->CTRLA.bit.SWRST = 1` will cause boot chaining to hang.
Setting the CPU clock to run from OSCULP32K during initialization is
all that is needed.
Signed-off-by: Jon Ringle <jringle@gridpoint.com>
Issue an upstream read transaction through uncached memory to flush
out all pending transactions before power down the host domain.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Fixes: #69785
The boards_legacy sub-folder was temporarily introduce in collab-hwm
branch during porting to HWMv2.
This should have been removed before merging collab-hwm to main as it
prevent looking up boards in oot roots.
Removing the temporary sub-folder for HWMv2.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Clean up early days TF-M development directives which are outdated today.
Factorize remaining CMake instructions in soc.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Replaces inaccurate or wrong vendor prefixes in board and soc
folder names with those from thr vendor prefix file
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Move the Kconfig symbols SOC_ESP32_PROCPU, SOC_ESP32_APPCPU,
SOC_ESP32S3_PROCPU, and SOC_ESP32S3_APPCPU.
The CPU cluster is defined in espessifc/soc.yml and should therefore
be available in the HWMv2 Kconfig.soc tree.
This will allow sysbuild to test for the CPU cluster when targeting
remote board for a build.
Update espressif boards accordingly.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Interrupts should not be enabled this early in boot time.
Driver initializations expect IRQs not to arrive when
setting up HW.
Remove enabling `MSTATUS.MIE` in `__start`.
It will be enabled when main thread is switched to,
as threads by default start with enabled `MSTATUS.MIE`.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
Due to HW issue, VPR needs to keep MSTATUS.MIE enabled during sleep.
Otherwise, interrupts will not wake it up.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
MEMC_MCUX_FLEXSPI depends on code relocation being enabled on parts that
XIP from the FlexSPI by default and requires a string describing the RAM
region to relocate code into. Add these Kconfigs to the RW SOC port.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This patch updates the power status register bitfield definitions in the
power management header for the Intel ADSP ACE 2.0 LNL platform.
Modifications include:
- Adjusting the 'ioxpgs' field from 4 bits to 2 bits.
- Adding a 'rsvd11' field with 2 bits to reflect reserved space.
- Changing the 'mlpgs' field from 2 bits to 1 bit.
- Updating the 'rsvd14' field from 1 bit to 2 bits for alignment.
These changes ensure that the power status register bitfields match the
latest hardware specification for the ACE 2.0 LNL SoC, which is crucial
for accurate power domain status monitoring.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
In the interrupt pending routine, only the interrupt status needs to be
cleared at the end of the interrupt routine. There is no need to do a
hardware reset(HALT) to avoid clearing the next transfer interrupt when
the current transfer is completed.
Test: Testing this function does not cause I2C data/clk to get stuck on
the system platform.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add support for propagating SOC_NRF54LX_DISABLE_FICR_TRIMCNF and
SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE values to nrfx.
Signed-off-by: Magdalena Pastula <magdalena.pastula@nordicsemi.no>
Previous adjustments to hwmv2 lost this Kconfig file.
Test: west build -p always -b it82xx2_evb samples/hello_world
config BOARD_IT82XX2_EVB
select SOC_IT82302_AX
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
When non-primary core is powered down and restart with sequence of:
- PM state set to SOFT_OFF
- once target core is idle, cut power with soc_adsp_halt_cpu()
- power up core again with k_smp_cpu_resume()
The execution will continue from stored DSP core context, but
will hit an assert in z_smp_cpu_mobile() as the PS.INTLEVEL
is zero.
Fix this issue by storing and restoring PS register in this flow.
Link: https://github.com/zephyrproject-rtos/zephyr/issues/70181
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The core clock of 8ULP's HIFI4 DSP runs at 475.2MHz. As such,
correct the value of `CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC` to
reflect this.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Transition to a low power DMI L1 state should be allowed only after all
pending DMA channels transfers have started.
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Dependencies of NXP_IMXRT_BOOT_HEADER were set incorrectly for the
RT11xx series part when building a dual core image. The boot header
should be enabled by default for the primary M7 core, and always
disabled when MCUBOOT is used or the M4 core is targeted
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
