Since bd9836be8c
the native logger is enabled always (even if a UART is present)
as it was though more conveniant for users.
But the documentation was not updated to reflect this.
Let's fix it.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The UP Squared board comes with different CPUs where Atom ones
run at 1.6GHz while the Pentium and Celeron ones run at 1.1GHz.
Since the APIC TSC Deadline timer driver is tied to the CPU
speed, and we were using 1.6GHz as the hardware clock speed,
real world time would not be correct for Pentium and Celeron
based boards (i.e. 1 second sleep requested in application does
not translate to 1 second in real world). Change it to use HPET
timer instead as HPET has the same clock rate for all board
variants. Applications requiring more precise clock rate can
override this in their configuration.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Support of stm32h5 targets with pyocd is required to allow debugging.
Provide runner configuration and update board documentation.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Commit 940c66f82e added a bunch of
ACPI PNP ID to x86 boards but skipped those for ACRN. And commit
34a2fbfba1 changed the behavior of
PCIe controller to looking for PNP ID, it results in compilation
error due to build asserts. So add the PCIe controller node to
the ACRN base DTS file.
Fixes#68956
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The nRF54* SoCs are in a very early stage of production and the software
supporting them is to be considered experimental. Document this
accordingly in the respective boards.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
If slots partitions are defined, related chosen should be configured.
Fixes build issue in samples/subsys/usb/dfu
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Prevent overrunning the irq vector table.
This is not happening today in tree, but coverity thinks it
may. Checking for it to prevent it is not a bad idea
anyhow, so let's do it.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
i2c pads were incorrectly configured and failed to work when testing
against an external fram part. Correct the i2c pinctrl settings for
arduino i2c to match other boards in the mimxrt lineup.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Change reset pin polarity for MIPI DBI SPI controller, so that the board
devicetree is responsible for setting the GPIO to active low, and the
driver always sets the pin to a logic 1 to reset the display.
Fixes#68562
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The yaml uses `arch: riscv` while other boards specify either
`arch: riscv32` or `riscv64`.
Unify this by changing the value to `riscv32`.
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
Previously the boot_write_img_confirmed() function used the MCUboot
public API function boot_set_confirmed(), but this function is hardcoded
to set the confirmed flag of slot 0. This works for MCUboot swap modes
but not for Direct XIP, where applications can execute out of secondary
slots.
This commit changes boot_write_img_confirmed() to instead use
boot_set_next() which sets the confirmed flag for a given flash area
and works with Direct XIP.
DT_CHOSEN(zephyr_code_partition) is used to get the current partition.
The zephyr,code-partition chosen node must be defined.
This commit also adds the zephyr,code-partition chosen node to the
native_sim devicetree to allow the tests under tests/subsys/dfu to
build for this target.
Signed-off-by: Ben Marsh <ben.marsh@helvar.com>
The DRAM range 0xc0000000~0xcfffffff is reserved for the Ethos-U NPU,
so change the RAM base to 0xd0000000.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
remove legacy modem properties and add modem node
compatible to modem subsystem, rak5010_nrf52840
has two variant, one with BG95-M3 and other is
BG96 modem, both are pin to pin compatible.
Signed-off-by: Karthikeyan Krishnasamy <karthikeyan@linumiz.com>
Define the reg and size property for the stm32 disco kits
which have an octospi instance
Refer to the dts/bindings/flash_controller/st,stm32-ospi-nor.yaml.
Also remove the <size> property for the stm362h750 disco kit.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Display is not working on STM32F429i-DISC1 board because
display_blanking_off() needs to be sent to ILI9341 device, but it's sent
to LTDC instead which does not implement it.
This patch adds a LTDC DT property that provides the pHandle of the
display's own controller so that display_blanking_off/on are forwarded to
it when they are called by an application.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Add a board that allows to build for the nRF54H20 PPR RISC-V core.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Because both, RISC-V and ARM cores share the same pinctrl driver. The
top level common folder will disappear with the introduction of HWMv2,
where multi-arch SoCs will be well supported.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add targets that allows building for the Application and Radio cores
in the nRF54H20 SoC on the nRF54H20 PDK board.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The mailbox peripheral is actively accessed by stm32_hsem functions,
so mark the device as enabled in DTS.
Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
Define the reg and size property for the stm32 boards with qspi inside
Refer to the dts/bindings/flash_controller/st,stm32-ospi-nor.yaml.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Define the reg and size property for the stm32u585 and stm32l562
disco kit.
Refer to the dts/bindings/flash_controller/st,stm32-ospi-nor.yaml.
The stm32l562 reads the sfdp table from the flash itself.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
1. Configure 'core-clock' to 192MHz to generate necessary 48MHz
2. Support workaround to disallowing ISO IN/OUT EPs to be assigned
the same EP numbers
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
drivers: eth: phy: tja1103: Handle link change
These changes enable -
TJA1103 driver to gracefully handle Link connect or disconnect events
between Ethernet PHY and its link partner and notify it to the
upper network layers
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
The DMA is already enabled for this board, but updating the board doc
page to make that clear, and enabling the DMA loop_transfer test.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
GR716A has two SPIMCTRL SPI controllers.
This adds the SPIMCTRL description to the DTS and makes the SPI
option available in the kernel configuration.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Add support for ADI EVAL-ADIN2111EBZ.
Tested samples:
* hello_world
* blinky
* dhcpv4_client
Co-developed-by: Philip Molloy <pmolloy@baylibre.com>
Signed-off-by: Philip Molloy <pmolloy@baylibre.com>
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
Add support for ADI EVAL-ADIN1110EBZ.
Tested samples:
* hello_world
* blinky
* dhcpv4_client
* adt7420
Tested proper SPI detection of the ADIN1110 chip.
Co-developed-by: Philip Molloy <pmolloy@baylibre.com>
Signed-off-by: Philip Molloy <pmolloy@baylibre.com>
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
Microchip's PolarFire SoC interface with on-board spi
nor flash via system controller. This on-board spi nor flash can be
used to store FPGA design bitstream's.
Signed-off-by: Harshit Agarwal <harshit.agarwal@microchip.com>
qemu_x86_tiny@768 has coverage enabled by default. Because of
this, it requires more stack space for running tests.
The increases needed are verified via twister.
Fixes#68272
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Convert ili9xxx display drivers to use MIPI DBI API. Due to the fact
this change requires a new devicetree structure for the display driver
to build, required devicetree changes are also included in this commit
for all boards and shields defining an instance of an ili9xxx display.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
add acpi pnp/hw id for pcie node to enable support for retreive
interrupt routing information for pci legacy interrupt via acpi
Signed-off-by: Najumon B.A <najumon.ba@intel.com>
We need to enable this configuration for all R-Car ARM64 boards.
First and foremost, we definitely should run Zephyr on the boards
in the NS-EL1 state. The EL3 is used for TF-A, EL2 is used for
U-Boot, and Xen in the case when we run Zephyr as Dom-0. The S-EL1
is used for OP-Tee, and S-EL0 is used for OP-Tee apps.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
On the Polarfire SOC Icicle Kit the SPI pins are routed to MikroBus.
Enable SPI by default.
Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
the device tree offers a default config (qdec0) for 1x qdec at TC0,
however does not offer a default config for qdec1 - qdec3.
this will be added with this commit. Fixes#65610
Signed-off-by: Sven Ginka <sven.ginka@gmail.com>
The purpose of this separation is to avoid conflict initializing
gpio-keys because button 0 and joystick up have a shared interrupt
source. Joystick is now configured using polling mode option.
Signed-off-by: Joel Guittet <joelguittet@gmail.com>
This allows to run tests & examples on the physical board with:
```
west twister -p mps2_an521 --device-testing --device-serial /dev/ttyUSB0
```
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Create a folder for RZ Renesas range device tree to follow how it's
done for other renesas ranges.
It will also help to better delimit areas to maintain.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
- Remove hadcoded cc2538-bsl.py path
- Use cc1352-flasher program instead
- Add docs about how to install the program
Signed-off-by: Ayush Singh <ayushdevel1325@gmail.com>
