Commit graph

5 commits

Author SHA1 Message Date
Filip Kokosinski 28c7674c66 dts/riscv: add riscv compatible string where it's missing
This commit adds the `riscv` compatible string to cpu nodes where it is
currently missing. This is convention is already followed by some cpu
nodes.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2024-01-31 10:41:49 +01:00
Franciszek Zdobylak 3975b4596f dts: riscv: niosv: Fix status string
Change malformed status string "disable" -> "disabled".

Signed-off-by: Franciszek Zdobylak <fzdobylak@antmicro.com>
2023-09-19 15:23:36 +01:00
Filip Kokosinski 806c95163a dts/riscv: add missing riscv,isa fields and modify existing ones
This commit adds/modifies `riscv,isa` strings using the following rules:
* the ISA string is lowercase
* multi-letter extensions are preceded with the underscore mark
* if an extension is implied by another one, it is not specified - e.g. the
  D extension implies the F extension, so writing `rv32ifd` is redundant

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2023-09-14 14:34:34 +02:00
Khor Swee Aun ad6bf7f456 dts: riscv: Add dts support for INTEL Nios V/g
Add basic dts support for INTEL Nios V/g General Purpose Processor.

Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com>
2023-06-17 07:34:05 -04:00
Khor Swee Aun 938b152b03 dts: riscv: Add dts support for INTEL NIOSV
Add basic dts support for INTEL NIOSV Microcontroller Core Processor.

Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com>
2023-02-20 09:29:13 -05:00