Commit graph

166 commits

Author SHA1 Message Date
Martí Bolívar 55f4075f92 dts: intel: cavs25: hack around awkward DT representation
Apparently, downstream drivers are allocating devices using
DT_NODELABEL(alh0) and DT_NODELABEL(alh1) on a node with compatible
intel,alh-dai. These represent something like "channels" within the
device.

This is a strange choice. It would be better to do something like have
a property with the count of "channels", or one child node per
channel.

It is also a dtc error to have duplicate node names like this, and
will be an error in Zephyr's dtlib soon.

For now, work around this representation issue by replacing it with
something equivalent that doesn't have duplicate nodes. The
representation should be addressed at some point, but not by me.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2022-09-21 07:55:40 -07:00
Lauren Murphy 85445474f2 boards, dts: fix filenames and dts refs for adsp clock
Changes filenames and DTS references from CAVS clock to
ADSP clock.

Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
2022-09-14 07:23:08 -04:00
Lauren Murphy 1983a4c50c boards, dts: fix namespace for intel adsp cavs, ace
Fixes namespace for Intel ADSP CAVS and ACE boards.

Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
2022-09-14 07:23:08 -04:00
Ederson de Souza fcdc9c78e2 soc/xtensa/intel_adsp: Get register address from DTS
Instead of hardcoding it where it's used.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-09-08 18:03:33 -04:00
Ederson de Souza 03a947850d drivers/mm: Get some bit configurations from DTS instead of SoC version
Migrate information to DTS and get it from there on the code. Note that
for CAVS 15, the information is not migrated as there's no DTS entry for
it. It can be brought back (in the DTS) if TLB support is enabled for
it.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-09-08 18:03:33 -04:00
Andrey Borisovich c75e6cfcb9 soc: intel_adsp_ace1x: Added IPC/IDC implementation
Added IPC and IDC implementation for Intel ADSP ACE1X SoCs.

Co-authored-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-09-06 15:33:24 -04:00
Piotr Kmiecik 0acd68247f drivers: ace_v1x wallclock driver
Wallclock driver with functionality required by ACE v1x base firmware.

Signed-off-by: Piotr Kmiecik <piotrx.kmiecik@intel.com>
2022-09-06 17:44:03 +02:00
Andrey Borisovich 2e04bfdfe0 soc: intel_adsp: Refactored IPC/IDC
Changes to code:
1. Renamed CAVS_IPC API from common/include/cavs_ipc.h to
common/include/intel_adsp_ipc.h. Renamed all API functions and structs -
added "intel_adsp_" prefix.
2. Moved definitions from intel-ipc-regs.h and ace-ipc-regs.g to SOC
specific headers include/<soc_name>/adsp_ipc_regs.h.
3. Added new common intel_adsp_ipc_devtree.h header with new
macros to retrieve IPC and IDC nodes and register addresses.
Put those new macros in code replacing hardcoded values outside of
devicetree.
4. Changed documentation of IDC and renamed IDC register struct
to have common name between all intel adsp socs.
5. Removed excessive docs description on cAVS IPC protocol.

Changes to Devicetree:
1. Renamed in all CAVS boards .dtsi files content in IPC nodes:
   - "cavs_host_ipc" node labels to "adsp_ipc" labels.
   - compatible "intel,cavs-host-ipc" renamed to
     "intel,adsp-host-ipc".
2. Added (previously missing) yaml file for "intel,adsp-host-ipc"
   compatible.
3. Renamed in all CAVS boards .dtsi files content in IDC nodes:
   - "idc" node labels to "adsp_idc" labels.
   - compatible "intel,cavs-idc" renamed to "intel-adsp-idc"
4. Renamed intel,cavs_idc.yaml file to intel,adsp_idc.yaml
   so it is suitable for both CAVS and ACE SoC family.
   Moved it from ipm bindings to ipc bindings where it belongs.

Changes to Kconfig:
1. Renamed existing Kconfig option CONFIG_CAVS_IPC to
   INTEL_ADSP_IPC.
2. For renamed INTEL_ADSP_IPC addded default value based on
   status of the "adsp-ipc" and "adsp-ipc" node.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-09-02 08:18:32 -04:00
Tomasz Leman 50452e6ad0 intel: adsp: enable d0i3 in device tree
This patch adds D0i3 definition to available core power states in device
tree.

Additionally, changing the name of the OFF state to better reflect what
is in the documentation.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2022-09-02 10:53:52 +00:00
Sylvio Alves 6946d441a8 Revert "soc: esp32: fix flash write blocks size"
This reverts commit fdd47f39be.

After v4.4.1, write-block-size is no longer needed to be 32-bytes

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-09-01 21:48:18 +00:00
Kumar Gala fab8d25fd3 drivers: mm: Add dts binding specific for ADSP Meteor Lake TLB
Add a specific compatiable and binding for intel,adsp-mtl-tlb.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-31 11:17:37 -05:00
Tom Burdick efc0928570 dma/hda: Use the correct register block size for each IP block
Previous versions were using, incorrectly, the host in/out regblock size
of 40 bytes for all peripherals when in fact the link in/out regblock size
is 20 bytes in size.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-08-18 14:54:57 -05:00
Felipe Neves a5379b71f8 drivers: ipm: ipm_esp32: remove hardcoded nodelabels
by making shared memory property  of IPM binding.

Signed-off-by: Felipe Neves <felipe.neves@linaro.org>
2022-08-16 18:06:02 +02:00
Felipe Neves 4bff7ecab3 drivers: ipm: esp32: added IPM driver
implemented by software for esp32 dual core
variants.

Signed-off-by: Felipe Neves <felipe.neves@linaro.org>
2022-08-16 18:06:02 +02:00
Krzysztof Frydryk 8dd57467cc drivers: dai: Enable Zephyr runtime power mgmt in Intel SSP driver
Enable Zephyr device runtime power management mechanisms in Intel SSP
driver. This allows Zephyr to track usage reference for power
domain gating.

Signed-off-by: Krzysztof Frydryk <krzysztofx.frydryk@intel.com>
2022-08-10 11:58:45 +02:00
Krzysztof Frydryk 078de4e021 power_domain: Intel ADSP: Add power gating mechanism for Intel ADSP devices
This adds power domain gating mechanisms for Intel ADSP devices.

Signed-off-by: Krzysztof Frydryk <krzysztofx.frydryk@intel.com>
2022-08-10 11:58:45 +02:00
Krzysztof Frydryk cbeebe5db6 dts: ace1x: Add lps address
Add lps address to ace 1.x devicetree.

Signed-off-by: Krzysztof Frydryk <krzysztofx.frydryk@intel.com>
2022-08-10 11:58:45 +02:00
Lucas Tamborrino ca9126fa81 dts: esp32/s2: add bindings to pcnt peripheral
Add pcnt node to esp32 and esp32s2.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2022-08-08 10:51:41 +02:00
Henrik Brix Andersen 9ca851721e dts: xtensa: espressif: esp32: add twai devicetree node
Add devicetree node for the ESP32 TWAI CAN controller.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-07-30 17:32:04 +01:00
Anas Nashif 6e57a57c53 intel_adsp: ace: reduce hda dma channels
This configuration does not work on some variants (simulator), reduce
the number to something that work on all variants.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-28 15:48:00 -04:00
Ederson de Souza 49d1583e2a soc/xtensa/intel_adsp: Enable WOVCRO based on platform support
Instead of enabling WOVCRO clock based on the SOC, use a configuration
to indicate support, so that each platform can specify if WOVCRO is
supported or not.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-07-28 11:04:05 -04:00
Glauber Maroto Ferreira 54710ddc83 esp32: dts: add RTC timer node
- add RTC timer node bindings
- add RTC timer node to the DT.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2022-07-27 09:48:33 +02:00
Kumar Gala 136960e071 dts: xtensa: Remove label property from devicetrees
Label properties are not required.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-26 12:57:35 -05:00
Tom Burdick c225cf3b8a dma: HDA rename prefix from cAVS to ADSP
HDA is a common IP used across the entire ADSP line and deserves
a name respecting that alongside similiar IP drivers such as the
ADSP GPDMA driver.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-07-14 17:53:46 +00:00
Lucas Tamborrino eca365929b dts: esp32: add bindings to mcpwm driver
add new pwm driver based on the mcpwm peripheral

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2022-07-14 10:29:26 +02:00
Tom Burdick 3824024f77 dma: hda link driver fixups
Fixes configured DMA direction for HDA link in/out drivers.

Adjusts the number of channels for link in/link out to safe value
that seems to work on all tested parts.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-07-13 10:55:17 -04:00
Glauber Maroto Ferreira 00f3582d89 soc: esp32: dts: counter: add properties and update dt
- adds properties 'group', 'index' and 'prescaler'.
- updates board's dts to include those properties.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2022-07-13 15:53:04 +02:00
Flavio Ceolin ad8ae7f735 dma: intel: Merge cavs and ace gpdma
cAVS and ACE gpdma driver have several similarities. This commit merge
this two drivers into a single one for Intel ADSP devices.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-11 10:21:17 +02:00
Anas Nashif b161554ee8 soc: cavs15: disable hda link in/out
This seems to cause a crash when running tests/boards/intel_adsp/hda and
also causing issues downstream on SOF.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-08 22:40:12 -04:00
Tom Burdick 572ccd531d intel_adsp: Use device tree to enable/disable each HDA driver
Uses the dt_compat_enabled Kconfig preprocessor to set defaults
for each HDA driver.

Each direction is uniquely selectable which can be useful when building
with SOF where only some directions may wish to be enabled at any given
time.

By default, given the device tree (intel_cavs.dtsi) only the host
directions are enabled but an overlay may adjust that as needed.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-07-08 14:33:06 -04:00
Flavio Ceolin 158a87018c intel: adsp: Simplify PM
Both idle and suspend states were just being used to set the cpu
idle. That is not necessary, if the pm policy does not find a suitable
power state the kernel automatically calls k_cpu_idle().

This remove unnecessary code and the weirdness of having
min-residency-us set to 0 and other arbitrary values.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-07 02:10:11 -04:00
Anas Nashif b330a05539 intel_adsp: add a new series to support Meteorlake
Meteorlake support as part of the Intel ADSP family.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Co-authored-by: Michal Wasko <michal.wasko@intel.com>
Co-authored-by: Konrad Leszczynski <konrad.leszczynski@intel.com>
Co-authored-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Enjia Mai <enjia.mai@intel.com>
Co-authored-by: Flavio Ceolin <flavio.ceolin@intel.com>
Co-authored-by: Tomasz Leman <tomasz.m.leman@intel.com>
Co-authored-by: Bonislawski Adrian <adrian.bonislawski@intel.com>
Co-authored-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Co-authored-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-07-06 15:11:07 -04:00
Lucas Tamborrino 02675bbc80 dts: esp32: full ledc configuration in binding
This commit moves the hardware configuration for ledc
peripheral to the device-tree instead of Kconfig.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2022-06-29 14:48:25 +00:00
Tom Burdick 34a76f1da4 dma: Intel HDA buffer alignment property
Bindings for Intel HDA now require the buffer alignment property to be
set.

Sets the property to 128 bytes for the common Intel cAVS device tree as
was implied by the tests cases.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-06-27 12:46:11 +02:00
Ederson de Souza 0ce9446978 soc/xtensa/intel_adsp: Add cAVS clock driver
Simple driver that allows one to choose the clock speed of xtensa cores.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-06-27 12:42:04 +02:00
Sylvio Alves fdd47f39be soc: esp32: fix flash write blocks size
Current write block size does not guarantee proper
write operation, what might cause corrupted data.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-06-22 12:27:32 +02:00
Anas Nashif 798a552daf boards: intel_s1000_crb: remove board/soc
Remove the intel_s1000_crb board. it is no longer available or supported
in the zephyr tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-06-13 16:19:51 -04:00
Adrian Bonislawski 638cfbbdbf drivers: dai: add ALH dai driver
The ALH is an intermediary device, which acts as a hub and provides an
abstracted support for numerous sound interfaces (e.g. SoundWire).

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2022-06-05 14:27:15 +02:00
Glauber Maroto Ferreira d6e8474498 esp32/s2/c3: pinctrl: dts: move pinctrl node out of SoC bus
On Espressif SoCs, the pin controller is a virtual device.
Pin settings are actually controlled in a distributed way.
Therefore, that node does not belong to the SoC bus.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2022-05-13 11:25:58 -07:00
Gerard Marull-Paretas 0d85931315 dts: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all dts code to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to zephyrproject-rtos#45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 19:54:54 +02:00
Tom Burdick d5bf250c2b dts: intel_cavs: cavs15 custom base IP base addrs
cavs15 uses different base addresses for IP blocks than the rest
and thus needs its own configuration in device tree.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-05-03 18:50:25 -05:00
Henrik Brix Andersen 472d0de081 dts: xtensa: espressif: esp32: add GPIO map for accessing full GPIO range
Add a GPIO pass-thru map for accessing the full range (0 to 39) of ESP32
GPIO pins by their datasheet number.

GPIOs 0 to 31 are mapped to gpio0 while GPIOs 32 to 39 are mapped to
gpio1.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-04-28 10:26:40 +02:00
Glauber Maroto Ferreira 188e92e531 esp32/s2/c3: dts: uart: remove peripheral property
The pinctrl support made usage of the 'peripheral'
property no longer required.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2022-04-20 13:27:47 +02:00
Glauber Maroto Ferreira d06959c057 esp32/s2/c3: dts: remove pinmux node
remove the pinmux node from ESP32, ESP32-S2
and ESP32-C3 SoCs.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2022-04-20 13:27:47 +02:00
Glauber Maroto Ferreira 12f794a9f4 soc: esp32s2: dts: remove property "use-iomux"
which became deprecated when pinctrl came into stage.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2022-04-20 13:27:47 +02:00
Glauber Maroto Ferreira dbd747b7f0 dts: xtensa: esp32s2: add pinctrl node and bindings
to support implementation and peripheral usage of the pinctrl
driver API.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2022-04-20 13:27:47 +02:00
Glauber Maroto Ferreira 4986747156 esp32: dts: spi: remove property "use-iomux"
which became deprecated when pinctrl came into stage.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2022-04-20 13:27:47 +02:00
Glauber Maroto Ferreira 70d4a6c25e dts: esp32: add pinctrl bindings and definitions
to support implementation and peripheral usage of the pinctrl
driver API.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2022-04-20 13:27:47 +02:00
Tom Burdick 2f320730a1 dma/cavs_hda: Adds link in/link out compatibles
Adds hda link in and out drivers. The link in and link
out channels of HDA have small differences
with the host channels. Updates the existing
cavs_hda drivers and code to account for these
differences.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-04-18 19:19:40 -04:00
Jaska Uimonen fa1eb1d774 dts: add bindings and definitions for intel ssp
Add ssp (i2s) nodes for Intel ssp. Use them in intel_adsp15
and intel_adsp25.

Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
2022-04-14 11:42:08 -04:00