1) Allow use of interrup driven instance.
ROM implementation could be selected via dts compatiable.
2) Use UART rx fifo and timeout interrupt for end of message detection.
Added to decrease interrupts count on data reception
3) Use ESP_LL api.
Signed-off-by: Pavlo Hamov <p.hamov@venstar.com>
MCUXpresso SDK sets the drive strength of LPUART and LPI2C pins to 4 for
this SOC, versus 6 for most other RT10xx boards. Update the pinmux.c
file for mimxrt1010_evk to reflect this.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adds SPI support on LPSPI1 to the RT1010. LPSPI1 is available on pins
6, 8, 10, and 12 of J57 on the evaluation board
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit enables the LPSPI1 peripheral on the RT1015 EVK. LPSPI pins
are not populated by default, but headers can be added to J19 on the EVK
to access these signals
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for LPSPI to mimxrt1024_evk. LPSPI1 is exposed on pins
6,8,10, and 12 of J19 of the evaluation board
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
SPI support is available on LPSPI1 and LPSPI3. Both of these require
board modifications to expose headers. LPSPI1 is used for testing,
and requires that the board have solder jumpers R278, R279, R280,
and R281 bridged.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
SPI support is available on LPSPI1 and LPSPI3. Both of these require
board modifications to expose headers. LPSPI1 is used for testing, and
requires that the board have solder jumpers R278, R279, R280, and R281
bridged.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
RT1050 has multiple LPSPI peripherals. The simplest to access is LPSPI1,
which can be connected by bridging solder jumpers on the board. Enable
this SPI peripheral, and set it as default for SPI tests.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This is the initial Zephyr support for Intel SoC FPGA Agilex support.
Agilex has quad-core 64-bit Arm Cortex*-A53.
This patch build Zephyr for Agilex development kit with 256KB SDRAM and
support hello_world sample code. The Zephyr will need to be loaded by
Intel Arm Trusted Firmware (ATF).
Agilex Zephyr boot flow:
FSBL:ATF BL2(EL3) -> SSBL:ATF BL31(EL3) -> OS:Zephyr(EL2->EL1)
Intel ATF can be loaded from:
https://github.com/altera-opensource/arm-trusted-firmware.git
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
PA11 can be remapped to PA9 by using the recently introduced
remap-pa11-as-pa9 property.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Enable i2c1 and i2c2 nodes on b_u585i_iot02a.
i2c1 is used as Arduino I2C
i2c2 is used as bus for HTS221 MEMS device.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This changes is an adaptation for the different boards
based on the SOC_STM32F412ZG that has been redifined
to SOC_STM32F412ZX
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The mimxrt10xx evaluation boards that support the NXP USDHC IP
communicate unreliably with SD cards at 1.8V using the USDHC driver.
This commit temporarily disables 1.8V communication for all rt10xx
boards that currently support the USDHC driver.
Fixes#32289
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This kconfig is only used for one board and is simply an alias
to another kconfig. So remove CONFIG_DW_ICTL_OFFSET and apply
the value directly to the other kconfig.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Remove Kconfig options for enabling device instances in favor of
taking that information only from device tree. Prior to that
change there was a mix of devicetree and Kconfig.
Bring back use of CONFIG_GPIO_NRF_INIT_PRIORITY.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Instructions to use openocd on stm32u5 based platforms were missing
an instruction on the branch to use.
Also, the console excerpt were not rendering correctly, so fix
them.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
HS6x nSIM doesn't have dcache_uncached_region property. Its presence
in configs (mdb.args) causes issues with 2021.06 nSIM, so let's
drop this property as it isn't used anyway.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
For some reason, LSE can't be used as LPTIM clock source
on nucleo_l073rz.
As a consequence, low power operations are not functional on
this platform.
Waiting for the original issue to be fixed, set LSI as LPTIM
clock source.
Partially fixes#38930
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Includes support for USB, CAN, ADC, DAC, and Arduino GPIO Map.
Future could support: ETM Trace (if Zephyr supports it), QSPI, FMC, DCMI
Initially based on closest BSP for the same SoC: nucleo_f446re
Extra peripherals added based on closest BSP for nucleo-144 board:
nucleo_f429zi
Checked against nucleo-144 schematic
Documentation updated as best as I could
Arduino compatible pinmux for SPI, UART and I2C via Zio header
Tested:
USB Device mode (samples/subsys/usb/console)
Console via ST-link usart3 (samples/hello_world)
user LEDs (samples/basic/blinky)
scripts/twister --device-tests -p nucleo_f446ze
Not tested but should work: SPI, I2C, CAN, ADC, DAC
Not working yet: Quad-SPI (missing in dts/arm/st/f4/stm32f4.dtsi)
Signed-off-by: Tom Owen <tom.owen@zepler.net>
This configures esptool, partition generator and
external bootloader build to use python tool defined
in Zephyr's context environment. This fixes error
regarding missing /usr/bin/python when python2.7 is not
installed in users's machine.
Partition table offset is also updated as part of
this change.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Adds flash partitions and chosen nodes to the mimxrt1020_evk device tree
to support mcuboot on the internal QSPI flash.
Also enables FlexSPI flash driver XIP mode support on this board to
support mcuboot.
Signed-off-by: Xabier Marquiegui <xmarquiegui@ainguraiiot.com>
This adds the uart4 device to the stm32f3_disco board
based on the stm32f303 device from STMicroelectronics
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The ITS needs a number of table, so HEAP must be reserved for runtime
allocation (1MiB is a round and convenient value):
- Redistributor:
* 64K table for all redistributors
* 64k for each redistributors
- ITS:
* 4K collection table aligned on 4K
* 4K x 128 device table aligned on 4K
This makes 11x64K to permit all allocations to success.
Note, will need 64K HEAP_MEM per CPUs added.
This doesn't necessarily include the Interrupt Translation Table,
which are 256bytes aligned tables, for reference a 32 ITEs table
needs 256bytes.
With 14x64K HEAP, up to 116 ITT tables of 32 ITEs can be allocated.
A specific HEAP_MEM_POOL_SIZE as been added to arm64_gicv3_its test
for the fvp_base_revc_2xaemv8a board to satisfy all memory allocation
constraints for 256 ITT tables with 32 ITEs allocations.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
By default fvp_base_revc_2xaemv8a used 17bits per DeviceID, limit it to
16bits for the PCIe MSI/MSI-C use-case and save some memory.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The gyro i3g4250d is added to the device tree of stm32f3_disco rev. E
and a yaml file for this revision to use in twister is added.
Signed-off-by: Jonathan Hahn <Jonathan.Hahn@t-online.de>
