Move to CMake 3.20.0.
At the Toolchain WG it was decided to move to CMake 3.20.0.
The main reason for increasing CMake version is better toolchain
support.
Better toolchain support is added in the following CMake versions:
- armclang, CMake 3.15
- Intel oneAPI, CMake 3.20
- IAR, CMake 3.15 and 3.20
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This is necessary to get some samples to link properly when moving
from device_get_binding() to DEVICE_DT_GET and friends. In particular
I ran into issues building i2c_fujitsu_fram without a real I2C device.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
1. Update soc.c file to add USB clock setup
2. Add a linker script file to move USB transfer
buffer and controller buffers to USB RAM
3. Update Kconfig's to add USB support
4. Add zephyr_udc0 nodelabel
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. Update soc.c file to add USB clock setup
2. Add a linker script file to move USB transfer
buffer and controller buffers to USB RAM
3. Update Kconfig's to add USB support
4. Add zephyr_udc0 nodelabel
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
USB devicetree nodes in Zephyr have different names,
mostly derived from the designations in data sheets.
Add zephyr_udc0 (USB device controller) nodelabel to
specific USB node to allow generic USB sample to be build.
Follow up on commit b4242a8 ("boards: add USB node aliases")
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
log and libc optimization default config are soc related
and should be moved out from board context.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
We have a 'mxicy' entry in vendor-prefixes.txt for this vendor. Use it
to be consistent. Linux's
Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml file allows
both, but I'd like to see what happens if we try to be consistent in
Zephyr. There isn't a binding for this compatible in zephyr, so I'm
hopeful this won't break any upstream use cases.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
These are using unknown vendor prefixes.
I did find references to a Nanjing Tianyi Hexin Electronics Co., Ltd.
on Crunchbase and I thought about adding a vendor prefix, but I can't
justify it since it's just a single board that is using it, and there
is no upstream driver.
Similarly, I found hynitron.com, which seems to be an electronics
vendor, but Google Translate says their "about" page translates to
"Incomplete website information, please contact sales" (and the
English version contains no text).
Just change ',' to '-' instead so there is no vendor prefix anymore.
We can revisit this if anyone wants to upstream drivers for these
compatibles in the future, but for now it doesn't seem worth it.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
These IP blocks' vendor is Cadence, whose proper vendor prefix is
'cdns' if we are going to match the Linux vendor prefixes list.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
It should be "maxim,max30101", because the vendor prefix for this
company is "maxim", not "max".
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
It should be "u-blox,sara-r4", because the vendor prefix for this
company is "u-blox", not "ublox".
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This commit adds the missing flash and RAM size properties for
mps2_an521 so that the integration tests that require large memory can
run on this board.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit adds the missing flash and RAM size properties for
native_posix and native_posix_64 so that the integration tests that
require large memory can run on this board.
Note that the flash and RAM sizes of 64MiB specified here is an
arbitrary value choosen to ensure that all currently supported tests
can run, since there is no inherent limit for the POSIX boards.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit adds the missing flash and RAM size properties for
sam_e70_xplained so that the integration tests that require large
memory can run on this board.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit adds the missing flash and RAM size properties for
frdm_k64f so that the integration tests that require large memory can
run on this board.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The commit that added this board forgot to add the simulation type and
the ARM FPU tests were being only built.
This commit adds the `simulation: qemu` property to enable running the
ARM FPU tests in QEMU.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Similar to commit 9512ae488a
("boards: remove USB option for nRF based boards")
Also remove not necessary UART_INTERRUPT_DRIVEN and
duplicate CONFIG_USB_UART_CONSOLE.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Thumb/ARM interworking causes problems with Zephyr's multiple link build
process when userspace is enabled. When compiling with userspace, the
first link process uses a dummy PROVIDE in the linker script for
z_object_find and z_object_wordlist_foreach. This dummy symbol is
treated as an ARM function call, but one of the calling functions is in
thumb mode. The compiler generates a veneer for thumb functions to call
z_object_wordlist_foreach. On the final link step, z_object_find and
z_object_wordlist_foreach are real functions and get compiled in thumb
mode, thus no veneer is generated in the text section. This means that
the .text size changes between the second and third link steps changing
the start of the devices section. That causes the kobject code to look
in the wrong spot for kernel objects and a crash ensues.
Workaround this for now by only compiling in ARM mode so that no veneer
is needed. Thus the section sizes stay the same during the different
linking steps.
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
QEMU supports the MPU on Cortex-R platforms so enable it for the
qemu_cortex_r5 platform. This allows running the mem_protect kernel
tests.
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
Adding board bl654_usb which is a Laird Connectivity BL654 module
mounted on a USB adapter.
Signed-off-by: Kieran Mackey <kieran.mackey@lairdconnect.com>
The qspi-nor flash is enabled.
Can be tested with e.g. drivers/spi_flash sample
Missing documentation of support of SPI and I2C added
Signed-off-by: Kim Bøndergaard <kim.boendergaard@escoglobal.com>
This commit disables the Cortex-M null pointer detection feature for
the QEMU mps3_an547 targets because QEMU permits bus access to the
unmapped 0x0-0x400 region used by the MPU-based null pointer detection
feature.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Now that SDK 0.13.0 is out we can enable QEMU support on the
MPS3-AN547 to get coverage on Cortex-M55.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
nucleo_l476rg:
adds tim3 with pwm on pb4, changes tim2 pwm pin from pa0 to pb10.
As a result timers are available on arduino pins D5 and D6.
nucleo_wb55rg:
adds tim1 with pwm on pa8, changes tim2 pwm pin from pa0 to pa15.
As a result timers are available on arduino pins D5 and D6.
Use default prescaler (==1) for 32-bit timer and
10.001 for 16-bit timers, as these are commonly used.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
nucleo_g0b1re:
removes spi2 from arduino header pins to ST morpho pins in order to
free pins for other peripherals.
Adds tim15 with pwm on pb14, changes tim3 pwm to pb4.
As a result timers are available on arduino pins D5 and D6.
nucleo g474re:
Adds timer 3 with pwm pin on pb4 and changes tim2 pwm pin
from pa5 to pb10.
As a result timers are available on arduino pins D5 and D6.
Use default prescaler (==1) for 32-bit timer and
10.001 for 16-bit timers as these are commonly used.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This migrates all the current iterable section usages to the external
API, dropping the "Z_" prefix:
Z_ITERABLE_SECTION_ROM
Z_ITERABLE_SECTION_ROM_GC_ALLOWED
Z_ITERABLE_SECTION_RAM
Z_ITERABLE_SECTION_RAM_GC_ALLOWED
Z_STRUCT_SECTION_ITERABLE
Z_STRUCT_SECTION_ITERABLE_ALTERNATE
Z_STRUCT_SECTION_FOREACH
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add ADC driver version 2 for MEC172x using new in-tree headers
and device tree properties. Update the ADC shell for the new driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
As 0.13 SDK is available and used in upstream verification by
default we can allow Zephyr toolchain for ARCv3 64bit boards.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
add a config CONFIG_QEMU_UEFI_BOOT to indicate whether
the qemu will use UEFI bootable method;
add a new test "sample.basic.helloworld.uefi" to verify
UEFT bootable method on qemu_x86_64 platform.
Signed-off-by: Chen Peng1 <peng1.chen@intel.com>
Microchip XEC has been using the standard NS16550 driver.
Using the standard NS16550 driver requires extra HW programming
for XEC UART in board level and did not support XEC GIRQ interrupt
programming. We add an XEC specific driver and remove UART specific
register programming from the board level and implement interrupt
support. Also, by implementing a SoC specific driver we can add
driver PM in the future.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
This change adds support to the cc1352r_sensortag for the hdc2xxx
temperature and humidity sensor introduced independently in #36342.
Fixes#36410
Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
To keep bisectability, cmake and west modifications
needs to be in sync.
cmake: update external project configuration
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
based on uart rom functions, also enable console driver
on top of this driver, which enables logging
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Some boards, e.g. atsamd20_xpro, enable non-minimal peripherals by
default like SPI. This goes against board porting guidelines, as it
enables a peripheral that is not necessarily used by all samples,
as discussed at #30694. This removes SPI as a default peripheral
for all sam/sam0 boards.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This is a follow-up to commit 3656ba5ae9.
Enable pull-up resistors on UART pins RXD and CTS in Nordic DK boards
where it is possible that these pins are not connected to anything on
the board and could generate problems if left floating (on some DKs
also the Interface MCU can be disconnected with the switch "nRF only",
hence pull-ups enabled also on uart0 for them).
Those pull-ups can still be disabled (by deleting the added properties)
if necessary to use a given board in some specific hardware setup.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The 32KHz crystal used is a tuning fork crystal which can have a larger
clock drift over temperature than an AT cut crystal, therefore the LFXO
clock source error rate needs updating to account for this possible
drift over temperature.
Signed-off-by: Jamie McCrae <jamie.mccrae@lairdconnect.com>
The 32KHz crystal used is a tuning fork crystal which can have a larger
clock drift over temperature than an AT cut crystal, therefore the LFXO
clock source error rate needs updating to account for this possible
drift over temperature.
Signed-off-by: Jamie McCrae <jamie.mccrae@lairdconnect.com>
The 32KHz crystal used is a tuning fork crystal which can have a larger
clock drift over temperature than an AT cut crystal, therefore the LFXO
clock source error rate needs updating to account for this possible
drift over temperature.
Signed-off-by: Jamie McCrae <jamie.mccrae@lairdconnect.com>
The 32KHz crystal used is a tuning fork crystal which can have a larger
clock drift over temperature than an AT cut crystal, therefore the LFXO
clock source error rate needs updating to account for this possible
drift over temperature.
Signed-off-by: Jamie McCrae <jamie.mccrae@lairdconnect.com>
The 32KHz crystal used is a tuning fork crystal which can have a larger
clock drift over temperature than an AT cut crystal, therefore the LFXO
clock source error rate needs updating to account for this possible
drift over temperature.
Signed-off-by: Jamie McCrae <jamie.mccrae@lairdconnect.com>
Update the Microchip XEC pinmux driver to use system I/O
routine for read/write of registers instead of direct use
of volatile and CMSIS defines. Add GPIO port number to
bindings instead of using hard coded value from chip headers.
Modify SoC DTSI pinmux syntax, requires "pinmux: pinumx {..."
or the DT macros will not work. Since pinmux is used by MEC152x
we update its chip pinmux DT.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
It is enough to set the USB_DEVICE_STACK option to enable
USB device support.
Remove USB_DC_STM32 for mikroe_mini_m4_for_stm32 board
since it is already selected on SoC level.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
It is enough to set the USB_DEVICE_STACK option to enable
USB device support. Also the option USB_NRFX is not necessary
here because it is selected in drivers/usb/device/Kconfig anyway.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
The USB option alone only caused the driver to be built
and actually has no benefit. Remove it from *_defconfig files.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
based on uart rom functions, also enable console driver
on top if this driver enabling logging
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
Zephyr is now able to convert ELF binary to the EFI application for
launching directly from the EFI firmware. The bootloader is not needed
and the information about grub was removed.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
The default CONFIG_APIC_TIMER_IRQ_PRIORITY is 4, but it should be 1 for
ACRN. That's why the testcase failed due to no timer interrupt was
triggered.
And we also temporary adjust the testing IRQ for dynamic isr due to it
conflict with the IRQ of the APIC TSC deadline TIMER.
Fixes#36203.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
for up_squared board, we already support to use UEFI bootable
method to run zephyr tests, so update the document to use
this UEFI method, rather than legacy BIOS stuff.
Signed-off-by: Chen Peng1 <peng1.chen@intel.com>
Add watchdog support to the mimxrt685 platform.
The mimxrt685 platform is excluded from the watchdog
test case because the test case uses variables in the
noinit section that need to be retained through a reset
but the rt685 does not retain this memory through a
reset.
Signed-off-by: David Leach <david.leach@nxp.com>
* Move definition of flexspi_nor_config_t into soc/ dir so it can
be shared by all i.MX RT based boards.
* Use Kconfig symbol CONFIG_NXP_IMX_RT_BOOT_HEADER instead of
HAL define (which is set based on the Kconfig symbol)
* Rename board files to flexspi_nor_config.c since they
are already namespaced by the board dir.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This fixes an issue that surfaced with Zephyr v2.6.0,
where the GPIO driver has not completed initialization
when attempting to use it during POST_KERNEL with
KERNEL_INIT_PRIORITY_DEFAULT.
Signed-off-by: Alex Tsamakos <alex@actinius.com>
Add Atmel sam0 sercom[uart] pinctrl bindings and implements pinctrl at
driver level. It changes all sam0 boards to use new feature and remove
pinmux driver dependency for sercom[uart]. The samples that require a
binding were update to keep consistency and avoid errors.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Adds support for PWM LEDs (red, green, blue) to the mimxrt685_evk board
by adding devicetree nodes and aliases, and configuring the associated
pinmuxes. The red PWM LED is disabled by default because it's connected
to the same PWM channel as the blue PWM LED.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Some devicetre overlays do not reflect the recent rename to make NS
variants of boards with TF-M support have more consistent names; fix
it.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
On R-Car the Cortex R7 is usually not the boot processor.
This configuration file make use of the Cortex A57 processor,
to initialize the Cortex R7.
It boils down to few steps:
- Apply power to the Cortex R7
- Set the boot address for the Cortex R7
- loading a firmware
- releasing the Cortex R7 reset
This configuration file also rely on A57 bootloaders,
to initialize device, memory, and security groups.
This file has been tested on openocd 0.10.0+dev-01508-gf79c90268-dirty,
shipped with zephyr sdk 0.12.4, and on openocd master
65c9653cc768f77a5e8cf2af73e0f40d614bdec2.
Thread awareness is possible thanks to this patch:
http://openocd.zylin.com/#/c/6369/
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Various non-secure variants of boards with SoCs that have Trusted
Firmware M support were recently renamed without any deprecations
added for the old names. This unnecessarily breaks the build for out
of tree users.
Fix that by adding the following deprecations (deprecated name ->
replacement name):
bl5340_dvk_cpuappns -> bl5340_dvk_cpuapp_ns
mps2_an521_nonsecure -> mps2_an521_ns
musca_b1_nonsecure -> musca_b1_ns
musca_s1_nonsecure -> musca_s1_ns
nrf5340dk_nrf5340_cpuappns -> nrf5340dk_nrf5340_cpuapp_ns
nrf9160dk_nrf9160ns -> nrf9160dk_nrf9160_ns
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Provide configurations for the nRF52840 DK and nRF5340 DK boards.
Adjust the test to cover specifics of I2S peripherals on nRF SoCs
(need of starting RX and TX simultaneously, lack of internal loopback).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Running postbuild.sh script after TF-M builds is a command,
to be executed after build, not a post-build byproduct.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adds support for SDMMC in stm32h747i_disco.
This commit is tested with fat fs list file example in
samples/subsys/fs/fatfs.
Signed-off-by: Affrin Pinhero <affrin.pinhero@hcl.com>
Create version 2 of the MEC GPIO driver to support MEC172x to not
interfere with MEC152x. When the MEC172x ECIA interrupt aggregator
driver is ready, this driver will use ECIA for registering GPIO
interrupt callbacks instead of maintaining its own interrupt table.
Add V2 DT binding.
Add the Kconfig configuration settings for the MEC172x GPIO
V2 driver at the SoC and board level.
Add port id to DT allowing use of DT FOR EACH macro in the driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
LIS2DH12TR has an internal pull-up connected to SDA0 pin, while this pin
is connected directly to GND on PCB. This results in constant power
consumption, which can be prevented by disconnecting internal SDA0
pull-up. Do so by adding 'disconnect-sdo-sa0-pull-up' DT property, so
that accelerometer driver will send a proper command during boot.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Using GPIO_ACTIVE_HIGH explicitly says what is the active level of GPIO,
so prefer that instead of using 0.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Update Microchip XEC RTOS timer driver adding MEC172x support and
using more device tree properities in the driver. We must also update
the XEC counter driver to use the new GIRQ DT properties.
Add new properties to RTOS timer and RTC timer YAML. These two timers
are linked due to option using a high speed timer for kernel busy wait.
Add Kconfig logic for XEC RTOS timer to MEC172x SoC.
Enable the Microchip XEC RTOS timer in the MEC172x evaluation board.
Add device tree nodes for most peripeherals.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
This reverts commit 445a23a167.
This change was made with the incorrect assumption that using IBECC in
an ACRN VM is a valid use case. Turns out that ACRN will always manage
the IBECC access itself and the Zephyr driver is only useful for running
natively on the hardware.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Add driver implementation and header files for a MEC172x
aggregated interrupt driver. Enable the parent(ECIA) node
to have the driver initialize interrupt hardware for use.
Enable child nodes for those GIRQs used for aggregation.
Refer to chip documention for the list of GIRQs restricted
to aggregation and those which support direct mode.
Add chip level device tree node for MEC172x EC interrupt
aggregator parent and GIRQ children. Each child node contains
a list of sources representing the source bit position in the
GIRQ registers.
Add DT bindings for ECIA and GIRQ nodes.
Add build file(s) and configuration items for the MEC172x ECIA
aggregated interrupt driver. Add and enable the MEC172x interrupt
driver on the MEC172x evaluation board(EVB). Enable parent node to
initialize ECIA hardware. Child nodes are left disabled until a
future driver needs them.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
This commit adds support for SDMMC driver, Which
was missing. THi commit will solveserror SDMMC init
error on stm32l496g_disco boards.
Signed-off-by: Affrin Pinhero <affrin.pinhero@hcl.com>
This commit adds support for SDMMC driver,
Which was missing. THi commit will solves
error SDMMC init error on STm32F746G_DISCO
boards.
Signed-off-by: Affrin Pinhero <affrin.pinhero@hcl.com>
Add support for sam_e70_xplained, sam_v71_xult based on TC0 counter.
Note: TC module is a 16-bit counter. Even with slow, 32768 Hz input
clock the time span counted by the driver is short.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
This board has the capability to use SERCOM2 as an i2c
interface on pins 8 and 9.
This adds the neccessary pinmux settings and devicetree
node.
Tested with the i2c shell module.
Signed-off-by: Leonard Pollak <leonardp@tr-host.de>
This commit updates the supported features of stm32l5 and stm32wl boards
to match the devicetree configuration.
- add link to board defconfig and board.dts
- sort supported features table alphabethically by interface.
Additionally CRYP peripheral is added as supported feature to the
mikroe_mini_m4_for_stm32 board documentation.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
SRAM partitioning for non-secure should be done via a reserved-memory
node and not fixed-partitions. fixed-partitions is meant for flash
style devices.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The stm32l47r soc has a dma of type dma-v2, so the cells have
only 3 elements,. This adpat for the quadspi periph.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This adds the ability to create Ethernet bridges for connecting
separate Ethernet segments together to appear as a single
Ethernet network.
This mimics the Linux functionality of the same name.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Implement a clock control driver for Microchip MEC172x handling
configuring the 32 KHz input sources for the PLL and peripheral-32k
clock domains. MEC172x differs from MEC152x. MEC152x had one 32K source
for both PLL and peripherals. MEC172x allows the two domains to use
independent 32 KHz sources. Device tree updated to provide addresses
of hardware used by the driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
The exit latency for the standby state is available in
policy/policy_residency_cc13x2_cc26x2.c. Just copying it to the state
definition in dts.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Reformatted "Configuring a Debug Probe" to display only one of the
options at a time to improve reading flow, and split paragraph
instructions into an easy to follow list with emphasized differences
Signed-off-by: Julia Hathaway <julia.hathaway@nxp.com>
Reformatted "Configuring a Debug Probe" to display only one of the
debug probe options at a time to simplify text on screen when
following along
Signed-off-by: Julia Hathaway <julia.hathaway@nxp.com>
This commit enables ADC support for stm32l496g_disco
platform in device tree. VREF is configured to use
internal. Current VREF is 2.5V.
Signed-off-by: Affrin Pinhero <affrin.pinhero@hcl.com>
reuse the lpc's lpadc driver for rt1170, modify the dts and add
some macro to shield some code of LPC series. Also add the
board support inside the tests/drivers/adc/adc_api/src/test_adc.c,
and a dts node:zephyr,user inside
samples/drivers/adc/boards/mimxrt1170_evk_cm7.overlay
Signed-off-by: Crist Xu <crist.xu@nxp.com>
Added minimal device tree and board files to build Microchip
MEC172x. SOC layer stripped down to allow build for checking
compilation only.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
libc optimization changes regarding memset and memcpy
added by this 5d55730cf6
caused wifi driver issues, which won't
let device get IP address.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Define the subghz radio node in the module dtsi file, with the internal
RF switch connection and TCXO setting, and point at it from the
corresponding dev board file.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
This commit enables true rng for nucleo_f207zg platform. This has been
tested with tests/drivers/entropy/api and is working as expected.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
Add I2C bus initial support to Renesas R-Car SoC series.
Both I2C2 & I2C4 buses are supported on R-Car H3 board.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Do not enable the Arm SysTick driver by default. Instead, rely on the
default Kconfig settings for the Arm SysTick driver.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Determine the default CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC from devicetree
when using the Arm SysTick hardware timer.
When the NXP KE1xF SoC series is using the Arm SysTick as hardware
timer, the cycles/second will always be equal to the CPU core clock
frequency.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Adds a devicetree chosen node to the mimxrt1170_evk_cm7 board to link
Segger RTT and SystemView sections in DTCM by default. Enables the AHB
clock while the CM7 is sleeping to allow debug access to the TCM.
Note that automatic RTT control block detection may not search the DTCM
address region, therefore you may need to manually set the RTT control
block address or search range in the Segger host tools (SystemView or
RTT Viewer). For example,
$ JLinkRTTViewer -ra 0x20000000
Tested with:
- samples/subsys/shell/shell_module/
- samples/subsys/tracing/
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Align the capitalization of the term "Bluetooth Mesh" to Bluetooth mesh"
in the documentation. This is done to to match the new updated naming
convention done in Bluetooth SIG. In the upcoming spec versions, it its
used "Bluetooth mesh" with the lower case convention.
Signed-off-by: Ingar Kulbrandstad <ingar.kulbrandstad@nordicsemi.no>
This commit enables entropy support for nucleo_wl55jc.
Additionally it sets the PLL Q divider to 2, which was not set in
the board dts before.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit adds support for the seeed studio LoRa-E5 Dev board,
which is powered by a module based on stm32wle5jc soc.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The bootloader itself contains the i.MX RT6xx boot header, so we don't
need to duplicate it when building chainloaded applications.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds flash partitions and chosen nodes to the mimxrt685_evk device tree
to support mcuboot on the external octal SPI flash. This flash is rated
for 100K minimum program-erase cycles per sector, therefore this
partition configuration supports approximately 100K / (24576/8128) =
33073 upgrades.
Tested with samples/subsys/mgmt/mcumgr/smp_svr. The image swap takes
about a minute and a half to complete.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Refactors the i.MX RT600 SoC series to be more consistent with the i.MX
RT10xx SoC series by choosing a child node (external flash device) of
the FlexSPI bus for zephyr,flash.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add psci and more cpu nodes into fvp_baser_aemv8r.dts. The purpose
of it is perparing to support SMP.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
This commit updates the NS board variant from
`nrf9160dk_nrf9160ns` to `nrf9160dk_nrf9160_ns`
to maintain consistency across zephyr.
Signed-off-by: Kevin Townsend <kevin.townsend@linaro.org>
This commit updates the NS board variant from
`nrf5340dk_nrf5340_cpuappns` to `nrf5340dk_nrf5340_cpuapp_ns`
to maintain consistency across zephyr.
Signed-off-by: Kevin Townsend <kevin.townsend@linaro.org>
This commit update the NS board variant from
`v2m_musca_s1_nonsecure` to `v2m_musca_s1_ns` to maintain
consistency across zephyr.
Signed-off-by: Kevin Townsend <kevin.townsend@linaro.org>
This commit update the NS board variant from
`v2m_musca_b1_nonsecure` to `v2m_musca_b1_ns` to maintain
consistency across zephyr.
Signed-off-by: Kevin Townsend <kevin.townsend@linaro.org>
This commit update the NS board variant from `mps2_an521_nonsecure`
to `mps2_an521_ns` to maintain consistency across zephyr.
Signed-off-by: Kevin Townsend <kevin.townsend@linaro.org>
This commit update the NS board variant from `bl5340_dvk_cpuappns`
to `bl5340_dvk_cpuapp_ns` to maintain consistency across zephyr.
Signed-off-by: Kevin Townsend <kevin.townsend@linaro.org>
This commit enables spi1 in dtsi and updates the
documentation for nucleo_l552ze_q platform.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This commit enables usart3 channel on nucleo_l552ze_q platform.
This would also be used to test usart in dma mode with
tests/drivers/uart/uart_async_api.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This commit enables usart3 channel on stm32l562e_dk platform.
This would also be used to test usart in dma mode with
tests/drivers/uart/uart_async_api.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This reverts commit a6a7a0d888.
Both application and network core define the same pins for uart0.
The pins should not be used simultaneously by both cores.
Signed-off-by: Marek Pieta <Marek.Pieta@nordicsemi.no>
Activate optimizations for stm32h735g_disco which in the end
optimize the calls to ferror and fileno away.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
uart0 is used as default console output in Zephyr. Change prevents
assertion fail in default configuration of hci_rpmsg sample. The
failing assertion is related to enabling logger without backend.
Signed-off-by: Marek Pieta <Marek.Pieta@nordicsemi.no>
Instructions to build enviroment setup
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
The _PrepC() function is the standard risc-v way
of zephyr entry point, so let it call the z_cstart instead
of calling this function directly.
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
by adding the soc specific files such: soc initialization code,
linker scripts and support for esp32c3 devkitm
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
Move shared resources from m0 to common. This enable shared hardware
definition between the two cpu cores.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Standard Arduino CLK signal is on D13,
nucleo_l476rg board has been modified accordingly.
Need an overlay to use default x_nucleo_idb05a1 spin D3 (PB3)
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
